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Dec 18, 2019 NEWS
Dr Papavassiliou Keynote speaker at prestigious International Workshop

Dr Papavassiliou was the Keynote speaker at prestigious International Workshop on Microsystems held on the 18 December at International Hellenic University.

His talk 'Engineering the Nanoscale: Turning defects into features', was well received and focused on his work on memristors for Forte, the abstract is below.

 

Engineering the Nanoscale: Turning defects into features

A dreaded enemy of CMOS technology is gate leakage, initiated by a dielectric breakdown of the gate insulator. Breakdown becomes increasingly likely as dimensions shrink, gate oxides are reduced to a thickness of a few atoms and exotic materials are used to raise the gate insulator dielectric constant in order to maximise transistor gain. Dielectric breakdown is indeed the nightmare of young PhD students struggling to learn how to make microelectronics devices, and of IC design engineers whose
CMOS integrated circuits frequently die of electrostatic breakdown during manufacture.

The novel, very promising, devices called memristors, are nanoscale devices whose resistance changes to record the history of signals applied on them. Memristors are thin oxide layers destroyed by dielectric breakdown. The leaky gate oxides of yesteryear are starting to be useful for information
storage, both digital and analog!


In this talk we will talk about Memristors; we will show one way to turn dielectrically destroyed capacitors to useful devices. A design methodology for configurable circuit elements for use in Field Programmable Analogue Arrays is introduced. Memristors are used as analogue memories for the configuration information of adjustable monolithic circuit components, e.g. inductors, capacitors and gain elements. Memristor‐enabled tuneable blocks have the potential to simplify the design of Field
Programmable Analogue Arrays, increase their functionality and, as a result, promote their use. The discrete implementations of reconfigurable components achieve over a decade of component value adjustment range, and operational frequencies to 10s or even 100s of MHz. Both component adjustment range and other performance metrics are expected to significantly increase in eventual monolithic implementations.