Nguyen received his Bachelor degree from The University of Technology, Vietnam in 2007. He worked as a hardware design engineer at Renesas Electronics from 2007 to 2010. He then obtained his Master degree from Western Sydney University in 2012 and PhD from The University of Sydney, Australia in 2017. He currently is a Research Associate at the APT Group, The School of Computer Science, The University of Manchester. His research interests include ASIC/FPGA design, device characterisation and modelling.
The promising advantages of functional oxides, as researched in FORTE, could offer great opportunities to overcome the limitations in power, density and performance of reconfigurable fabrics. Our research is to exploit functional oxides to develop hardware architecture and design flow for a digital reconfigurable fabric. The current research is focusing on investigating memristor-based building blocks for reconfigurable FPGAs. These will then be used to develop a full memristor-based design flow for reconfigurable FPGAs
Jing received his Bachelor of Science degree from HKBU in 2011. Then he completed his Master of Engineering in 2013 and PhD in 2019 at RMIT University, Australia. He is currently working as a research associate at Department of Computer Science, The University of Manchester.
The current research is focusing on the development of memristor-based FPGA architecture. His research interest includes FPGA design, embedded systems and asynchronous logic.
Jianing Chen received a B.Eng.(Hons) degree in automatic control and systems engineering from the University of Sheffield, UK, in 2010, and completed his Ph.D. degree in systems and control engineering at the same institution, in 2015.
At present, he is working at the Micro-eletronics Design Lab, the University of Manchester.
His research interests lie in computer vision, self-organizing systems, and computational intelligence.