Memristive devices have elicited intense research in the past decade thanks to their inherent low voltage operation, multi-bit storage and cost-effective manufacturability. Nonetheless, several outstanding performance and manufacturability challenges have prevented the widespread industry adoption of redox-based memristive matrices. Here, we discuss these challenges in terms of key metrics and propose a roadmap towards realizing competitive memristive-based neuromorphic processing systems.

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

Electrophysiological techniques have improved substantially over the past years to the point that neuroprosthetics applications are becoming viable. This evolution has been fuelled by the advancement of implantable microelectrode technologies that have followed their own version of Moore’s scaling law. Similarly to electronics, however, excessive data-rates and strained power budgets require the development of more efficient computation paradigms for handling neural data in situ; in particular the computationally heavy task of events classification. Here, we demonstrate how the intrinsic analogue programmability of memristive devices can be exploited to perform spike-sorting on single devices. Leveraging the physical properties of nanoscale memristors allows us to demonstrate that these devices can capture enough information in neural signal for performing spike detection (shown previously) and spike sorting at no additional power cost.

In this study, we present the fabrication of wafer level micro-inductors, designed for contactless neuro-stimulation in vitro, along with an electrothermal study testing the influence of thermal phenomena to their performance. The electrical performance of all micro-scale electromagnetic components is hampered by two dominant factors: Joule heating and electromigration. The scope of the study is to evaluate how these phenomena change the electrical behaviour of the samples during activation. We experimentally define the safe area of operation across six types of samples with different geometric characteristics and we extract useful information for the reliability of the samples by comparing their median failure times. Our findings present the activation restrictions which should be taken into account in order to avoid the thermal degradation of the components, while at the same time could be used as design guidelines for similar geometries.

Resistive random access memories (RRAMs) are considered as key enabling components for a variety of emerging applications due to their capacity to support multiple resistive states. Deciphering the underlying mechanisms that support resistive switching remains to date a topic of debate, particularly for metal-oxide technologies, and is very much needed for optimizing their performance. This work aims to identify the dominant conduction mechanisms during switching operation of Pt/TiO2-x/Pt stacks, which is without a doubt one of the most celebrated ones. A number of identical devices were accordingly electroformed for acquiring distinct resistive levels through a pulsing-based and compliance-free protocol. For each obtained level, the switching current-voltage (I-V) characteristics were recorded and analyzed in the temperature range of 300 K–350 K. This allowed the extraction of the corresponding signature plots revealing the dominant transport mechanism for each of the I-V branches. Gradual (analogue) switching was obtained for all cases, and two major regimes were identified. For the higher resistance regime, the transport at both the high and low resistive states was found to be interface controlled due to Schottky emission. As the resistance of devices reduces to lower levels, the dominant conduction changes from an interface to the core-material controlled mechanism. This study overall supports that engineering the metal-oxide/metal electrode interface can lead to tailored barrier modifications for controlling the switching characteristics of TiO2 RRAM.

The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and affordable and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of standard characterisation protocols for fair benchmarking. At the same time, opportunities for innovation are missed by focusing on excessively narrow performance aspects. To that end our work presents a complete, technology agnostic, characterisation methodology based on established techniques that are adapted to memristors/RRAM characterisation needs. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to benchmarking across a variety of electrical performance metrics that can in turn support the generation of device models

The electrical properties of thin TiO2 films have recently been extensively exploited with the aim of enabling a variety of metal-oxide electron devices: unipolar and bipolar semiconductor devices and/or memristors. In these efforts, investigations into the role of TiO2 as active material were the main focus; however, electrode materials are equally important. In this work we address this point by presenting a systematic quantitative electrical characterization study on the interface characteristics of metal-TiO2-metal structures. Our study employs typical contact materials that are used both as top and bottom electrodes in a metal-TiO2-metal setting. This allows an investigation of the characteristics of the interfaces as well as holistically studying an electrode's influence on the opposite interface, referred to in this work as the top/bottom electrodes inter-relationship. Our methodology comprises the recording of current–voltage (I–V) characteristics from a variety of solid-state prototypes in the temperature range of 300 K –350 K, and their analysis through appropriate modelling. Clear field- and temperature-dependent signature plots were also obtained, so as to shine more light on the role of each material as top/bottom electrodes in metal-TiO2-metal configurations. Our results highlight that these are not conventional metal–semiconductor contacts, and that several parameters are involved in the formation of the interfacial barriers, such as the electrode's position (atop or below the film), the electronegativity, the interface states, and even the opposite interface electrode material. Overall, our study provides a useful database for selecting appropriate electrode materials in TiO2-based devices, offering new insights into the role of electrodes in metal-oxide electronics applications.

Biologically plausible neuromorphic computing systems are attracting considerable attention due to their low latency, massively parallel information processing abilities, and their high energy efficiency. To achieve these features neuromorphic silicon neuron circuits need to be integrated with plastic synapse circuits capable of on-line learning and storage of synaptic weights. Within this context, memristive devices play a key role thanks to their non-volatility, scalability, and compatibility with the complementary metal–oxide–semiconductor fabrication process. However, neuro-memristive systems are still facing difficult challenges for implementing efficient learning protocols. Here, we propose and demonstrate in hardware a spike-driven threshold-based learning rule which goes beyond conventional spike-timing dependent plasticity mechanisms, by also taking into account the neuron membrane potential and its firing rate. The mixed memristive–neuromorphic system we demonstrate comprises an oxide-based memristive synapse device placed between two silicon neurons implemented on a neuromorphic chip that comprises the proper interfacing and spike-based learning circuits designed to drive the memristive elements. We show how the system is able to emulate in real-time weight dependent post-synaptic activity and drive synaptic weight updates at the memristive synapse level following the spike-driven learning rule presented. We validate this spike-based learning mechanism with experimental results and quantify the system performance with basic learning experiments.

As the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Emerging nanoelectronics technologies bring forth new prospects yet a significant rethink of electronics design is required for realising their full potential. Here we lay the foundations of a design approach that fuses analogue and digital thinking by combining digital electronics with analogue memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and capable of performing analogue computation at a power cost close to digital. The versatility and benefits of our approach are experimentally showcased through a hardware data clusterer and an analogue NAND gate.

Environmental conditions can greatly affect the performance of semiconductor devices. Great sophistication has thus gone into developing versatile systems that allow benchmarking of operating characteristics under a variety of temperature and humidity conditions. Recently, Resistive Random Access Memory (RRAM) technologies, also known as memristors, have received a lot of attention for memory and computing applications. This interest is showcased by several reports on technology and applications developments, as well as developments on the underpinning infrastructure, i.e. models and characterization tools, that renders such technologies useful. Several international research groups and companies are nowadays using ArC One™, a versatile instrument that allows en masse characterization of RRAM technologies, as has been presented previously in several demo sessions at ISCAS. In this work, we present a newly developed module that expands ArC One™ capabilities through incorporating an environmental control system. The proposed module condenses the functionality of significantly larger, more complex and higher cost systems into a low cost, small form-factor and user friendly desktop-operated device. The system allows for temperature, atmospheric composition and humidity control and can be used for studying the impact of such settings on the electrical characteristics of RRAM technologies.

In this work we present an evaluation routine aimed towards assessing the multibit capability of Resistive Random Access Memory (RRAM) technologies. We illustrate a characterization methodology for the maximum possible exploitation of the resistive states of a RRAM cell. Our characterization routine consists of a three phase algorithm: during the first it infers the polarity needed to induce a change in the device's conductance; the second stabilizes the resistive states of the device into a baseline resistance and during the third a sequence of pulses of increasing amplitude is used to determine the actual resistive states. This technology-agnostic methodology allows for efficient and high resolution partitioning of the cell's resistive operating range allowing them to operate in a truly analogue fashion. Demonstrating the maximum potential of RRAM cells in terms of closely packed resistive states can open new avenues for research in non-volatile memories, reconfigurable electronics and neuromorphic applications.

The ability to read brain activity across large swathes of cortex at very high resolution both spatially and temporally is a holy grail objective of modern neuroscience. In this endeavour, the minuteness of neural signals arriving from needle probes (10s to 100s of μV) poses a significant challenge, typically solved using high spec amplifiers. However, when the objective is to detect neural spikes the input signals of interest are inherently sparse, and much energy is spent amplifying data points that will be ultimately discarded. In this work we propose that a possible solution is to distance ourselves from the need to amplify the neural waveforms, and instead opt for performing threshold detection directly on the input signal; which is often sufficient to detect neural spiking. We thus present a high sensitivity threshold detection circuit concept that uses its offset voltage as the reference threshold and thus directly transforms differential input signal samples into digital values. The use of memristive devices within the design allows us to finely tune the detector's offset voltage, thus ensuring sufficient operational flexibility. Using SPICE simulations we demonstrate an exemplar design built using our concept. First we shown its functionality and then we proceed to examine how: i) mismatch at strategically chosen devices affects the amplifier's offset voltage and ii) changing the resistive state of the memristive devices involved helps the designer control the offset voltage.

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include threshold logic and receptive field based classifiers that are presented within the context of a unified perspective.

We demonstrate an environmental control system for testing Resistive Random Access Memory technologies under accurately controlled humidity and temperature. The demonstrated system compresses the functionality of existing environmental control systems into a low cost, desktop-size solution, aimed at providing results quickly and with minimum installation and running overheads.

In this demo we present a comprehensive solution for benchmarking the multibit capabilities of resistive memory cells using sequential programming pulses. The algorithm is presented through a rich graphical user interface that allows the user to fully tune the benchmarking parameters..

With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.

Advanced neural interfaces mediate a bioelectronic link between the nervous system and microelectronic devices, bearing great potential as innovative therapy for various diseases. Spikes from a large number of neurons are recorded leading to creation of big data that require online processing under most stringent conditions, such as minimal power dissipation and on-chip space occupancy. Here, we present a new concept where the inherent volatile properties of a nano-scale memristive device are used to detect and compress information on neural spikes as recorded by a multielectrode array. Simultaneously, and similarly to a biological synapse, information on spike amplitude and frequency is transduced in metastable resistive state transitions of the device, which is inherently capable of self-resetting and of continuous encoding of spiking activity. Furthermore, operating the memristor in a very high resistive state range reduces its average in-operando power dissipation to less than 100 nW, demonstrating the potential to build highly scalable, yet energy-efficient on-node processors for advanced neural interfaces.