A Data-Driven Verilog-A ReRAM Model
A Data-Driven Verilog-A ReRAM Model
Open-Source RRAM Compiler
Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.
Introducing RRAM into the standard CMOS integrated circuit design flow
RRAM technology has experienced explosive growth in the next generation of nano-electronics, with multiple device structures being developed for a wide range of applications. However, this technology is only accessible to a handful of circuit designers, scientists and researchers where in-house fabrication and funds are available. Thus, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain such that circuit design and validation can be done before it is laid onto the wafer and integrated with CMOS.
Pt – TiOx – Pt
Process maturity: Stable TiOx-based memristors are the basic devices fabricated by our lab and have been used for many different papers and applications. They provide reliable non-volatile or volatile behaviour depending on the choice of electrodes and forming procedure. Depending on forming method volatile behaviour is still present even in formed devices. Items with (*) below indicate possibility for CMOS integration.
RRAM Technology