Our vision is to rejuvenate modern electronics by developing and enabling a new approach to electronic systems where reconfigurability, scalability, operational flexibility/resilience, power efficiency and cost-effectiveness are combined. 

Below is a list of our current publications helping us work toward our vision. 


March 2023
Flexible Oxide Thin Film Transistors, Memristors, and their Integration
Alin Panca, Julianna Panidi, Hendrik Faber, Spyros Stathopoulos, Thomas D. Anthopoulos, Themis Prodromakis
Flexible electronics have seen extensive research over the past years due to their potential stretchability and adaptability to non-flat surfaces. They are key to realizing low-power sensors and circuits for wearable electronics and Internet of Things (IoT) applications. Semiconducting metal-oxides are a prime candidate for implementing flexible electronics as their conformal deposition methods lend themselves to the idiosyncrasies of non-rigid substrates. They are also a major component for the development of resistive memories (memristors) and as such their monolithic integration with thin film electronics has the potential to lead to novel all-metal-oxide devices combining memory and computing on a single node. This review focuses on exploring the recent advances across all these fronts starting from types of suitable substrates and their mechanical properties, different types of fabrication methods for thin film transistors and memristors applicable to flexible substrates (vacuum- or solution-based), applications and comparison with rigid substrates while additionally delving into matters associated with their monolithic integration.
February 2023
Interfacing Biology and Electronics with Memristive Materials
Ioulia Tzouvadaki, Paschalis Gkoupidenis, Stefano Vassanelli, Shiwei Wang, Themis Prodromakis
Memristive technologies promise to have a large impact on modern electronics, particularly in the areas of reconfigurable computing and AI hardware. Meanwhile, the evolution of memristive materials alongside the technological progress is opening application perspectives also in the biomedical field, particularly for implantable and lab-on-a-chip devices where advanced sensing technologies generate a large amount of data. Memristive devices are emerging as bioelectronic links merging biosensing with computation, acting as physical processors of analogue signals or in the framework of advanced digital computing architectures. We review recent developments on the processing of electrical neural signals, as well as on transduction and processing of chemical biomarkers of neural and endocrine functions. We conclude with a critical perspective on the future applicability of memristive devices as pivotal building blocks in Bio-AI fusion concepts and bionic schemes.
February 2023
A study on the clusterability of latent representations in image pipelines
Adrian Wheeldon; Alexander Serb
Latent representations are a necessary component of cognitive artificial intelligence (AI) systems. Here, we investigate the performance of various sequential clustering algorithms on latent representations generated by autoencoder and convolutional neural network (CNN) models. We also introduce a new algorithm, called Collage, which brings views and concepts into sequential clustering to bridge the gap with cognitive AI. The algorithm is designed to reduce memory requirements, numbers of operations (which translate into hardware clock cycles) and thus improve energy, speed and area performance of an accelerator for running said algorithm. Results show that plain autoencoders produce latent representations which have large inter-cluster overlaps. CNNs are shown to solve this problem, however introduce their own problems in the context of generalized cognitive pipelines.
February 2023
Precise Characterizing of FPGAs in Production Systems
Bardia Babaei; Dirk Koch
The deployment of FPGAs in cloud data centers has entailed new security concerns. Although several defensive mechanisms are employed to detect and prevent malicious designs, a health monitoring tool can warn cloud service providers about the failure of implemented defensive fences. This PhD project aims to monitor the health status of internal FPGA resources by performing a precise timing characterization.
February 2023
Ultra-fine signal classification using memristor-enabled hardware (thesis)
Jiaqi Wang; Alexander Serb; Themis Prodromakis
Neural activity recording system promotes the development of diagnostic and therapeutic programs and neuroscience research. Direct recordings of neural signals from the brain have helped scientists access to study and unlock the secrets of neural coding gradually. This can be realised by applying implantable neural recording systems to monitor and record neural signals. Then, the neural information can be transmitted to the external device for processing, storage or application. However, the power consumption of the neural recording system is the primary constraint to monitoring large groups of neurons. It leads the development of neural recording systems in two directions: 'high-channel-count but wired' and 'wireless but low-channel-count'. To address the power issue, we proposed a neural front-end that aims to detect neural spikes by thresholding and output as one-bit digital data so that the afterwards processing can only work on spikes rather than processing all the data points. The most significant feature is that we induce memristors as trimming devices to tune the threshold voltage for spike detection. Meanwhile, it contributes to rejecting up to 50mV DC offset from electrodes. The measurement presents that the memristor-based pre-amplifier is capable of achieving above 95% spike detection accuracy with hundreds of nanowatt power consumption per channel. This design indicates a promising approach to conduct spike-detection on-chip with low power consumption and demonstrates the potential of a hybrid memristor/CMOS circuit for power-efficient large-scale neural interfacing application.
January 2023
RRAM, Device, Model and Memory
Abdulaziz Alshaya; Qihao Han; Christos Papavassiliou
The memristor is an innovative passive electrical device that has gained popularity in recent years as a potential candidate for next-generation non-volatile memory (NVM) and analog computing. This popularity stems from the memristor’s ability to store information in a manner that is inaccessible to external power sources. It is possible to electrically modify the resistance state, and this change will be retained even after the external bias has been removed. This is a distinctive electrical characteristic of the device. In this paper, we present a comprehensive presentation and illustration about SkyWater memristor device and model. A read/write operation for a standalone memristor (1R), and a 1 transistor 1 memristor (1T1R) were conducted. The RRAM successfully can be written and read 1-bit information by dividing the resistance of the memristor (memristance) into two states of RON=10.07 KΩ as a bit 1 and ROFF=3.38 MΩ as a bit 0.
January 2023
Passive Selectorless Memristive Structure with One Capacitor-One Memristor
Abdulaziz Alshaya; Qihao Han; Christos Papavassiliou
Memristor memory has garnered more interest as a potential future non-volatile memory. One access transistor and one memristor (1T1R) cell structure can be utilized to eliminate the issue of sneak path current in crossbar-structured memristor memories. However, it has lower switching speed and high-power consumption. In this paper, a novel passive selectorless structure cell has been studied. One capacitor-One Memristor (1C1R) structure is proposed as a passive access device that can be controlled by the applied signal width. The 1C1R successfully writes and reads 1-bit information with two resistance value: 3.38MΩ as bit 0, and 10.07KΩ as a bit 1. 1C1R topology is proposed as a promising structure that has lower power consumption and faster switching speed compared to 1T1R. In addition, this work addresses the readout technique with 1C1R structure. The RRAM is implemented by SkyWater Verilog-A model.
December 2022
High On/Off Ratio Carbon Quantum Dot-Chitosan Biomemristors with Coplanar Nanogap Electrodes
Niloufar Raeis-Hosseini, Dimitra G. Georgiadou, and Christos Papavassiliou
A carbon-based natural nanocomposite material comprising carbon quantum dots (CQDs) is dispersed in a chitosan matrix. The CQD–chitosan nanocomposite serves as a solid polymer electrolyte layer of a biomemristor with a Au/CQD–chitosan/Al structure. The active layer of the CQD–chitosan nanocomposite is deposited from its solution on top of coplanar asymmetric nanogap (∼15 nm) Al–Au electrodes, patterned via adhesion lithography. The CQD–chitosan biomemristor presents a high on/off ratio (>106) and reproducible and reliable bipolar resistive switching behavior. An endurance of 160 cycles was recorded, while the high and low resistance states remained stable for more than 104 s. This study highlights the potential of both the CQD–chitosan material and nanogap electrode structures for application in nanoscale biocompatible memory devices.
December 2022
byteman: A Bitstream Manipulation Framework
Kristiyan Manev; Joseph Powell; Kaspar Matas; Dirk Koch
From better resource pooling for FPGA cloud providers to building dynamic execution pipelines at runtime, the capabilities of partial reconfiguration (PR) are waiting to be fully explored. However, the community still fails to materialize PR at scale, and FPGAs are only used as updatable ASICs, hence, omitting the opportunities offered by dynamically reconfiguring FPGAs at runtime. This work proposes a resourceful FPGA bitstream manipulation framework. The proposed tool provides means for parsing, modification, and generation of bitstream files, and it has been open-sourced and demonstrated in a working system. As a distinguished feature, it supports multidie FPGAs (among the 106 Xilinx 7 Series, UltraScale, and UltraScale+ devices), and enables datacenter FPGAs to be used for relocatable PR. Using the versatile tool's built-in (dis)assembler allows for manual bitstream manipulations. Bundled with an efficient bitstream manipulation core, the efficacy is demonstrated by two case studies where we observe 58 - 377x higher bitstream merging throughput than a current state-of-art tool.
December 2022
Delta-Sigma Modulator Design Using a Memristive FIR DAC
Danyu Wang; Shiwei Wang; Themis Prodromakis; Christos Papavassiliou
This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator using a memristive finite impulse response (FIR) digital-to-analog converter (DAC) in the feedback. To achieve better power and circuit area efficiency, the coefficients of the 8-tap FIR filter are implemented using memristors with programmable resistance in the range of 17.20kΩ to 55.63kΩ . The modulator was designed and simulated using a 180nm standard CMOS technology in addition to a memristor model, which was constructed based on the measured characteristics of the real device behavior. The modulator targets 10kHz signal bandwidth and samples at 10MHz. Simulation results show that the FIR DAC can improve the modulator signal-to-noise and distortion ratio (SNDR) from 44.36dB to 62.29dB with the existence of 5ns RMS jitter at the sampling clock. The FIR DAC still contributes to a better modulator SNDR performance even considering a worst-case 20% resistance variation of the memristors.
November 2022
Multi-State Memristors and Their Applications: An Overview
Chaohan Wang; Zhaoguang Si; Xiongfei Jiang; Adil Malik; Yihan Pan; Spyros Stathopoulos; Alexander Serb; Shiwei Wang; Themis Prodromakis; Christos Papavassiliou
Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state (also often referred as multibit, and multi-level) switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multi-state memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multi-state memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.
November 2022
A High-Voltage Characterisation Platform For Emerging Resistive Switching Technologies
Jiawei Shen; Andrea Mifsud; Lijie Xie; Abdulaziz Alshaya; Christos Papavassiliou
Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.
November 2022
A Wide Dynamic Range Read-out System For Resistive Switching Technology
Lijie Xie; Jiawei Shen; Andrea Mifsud; Chaohan Wang; Abdulaziz Alshaya; Christos Papavassiliou
The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.
November 2022
Analogue Circuits Real-Time Emulation based on Wave Digital Filter
Abdulaziz Alshaya; Saleh Komies; Lijie Xie; Jiawei Shen; Christos Papavassiliou
Currently, we have no practical emulation solution for analogue and mixed-signal (AMS) circuits, unlike resolutions found for FPGA digital circuit emulation. This paper presents a high Q crystal oscillator circuit emulation based on Wave Digital Filter (WDF). An analogue circuit emulation method was used based on WDFs proposed in [1] to cover the entire flow of transforming an analogue circuit from a SPICE netlist towards FPGA hardware implementation. Although the WDF has been shown to be effective for circuits with linear elements, a proper method for dealing with nonlinear components, such as MOS transistors, is required. [2] proposed a WDF model for MOS transistors that can solve the connectivity problem in traditional nonlinear WDF models while maintaining analogue emulation accuracy and efficiency. As emulation examples, Resistor-Capacitor (RC), Common Source amplifier (CS), and high Q crystal oscillator circuits were implemented in WDF and compared to their SPICE simulations for verification purposes.
November 2022
Hybrid CMOS/Memristor Front-End for Multiunit Activity Processing
Jiaqi Wang; Alexander Serb; Shiwei Wang; Themistoklis Prodromakis
Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.
November 2022
Offset Rejection in a DC-Coupled Hybrid CMOS/Memristor Neural Front-End
Jiaqi Wang; Alexander Serb; Shiwei Wang; Themistoklis Prodromakis
One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.
November 2022
Hardware-efficient compression of neural multi-unit activity using machine learning selected static Huffman encoders
Oscar W Savolainen, Zheng Zhang, Peilong Feng, Timothy G Constandinou
Recent advances in intracortical brain machine interfaces (iBMIs) have demonstrated the feasibility of using our thoughts; by sensing and decoding neural activity, for communication and cursor control tasks. It is essential that any invasive device is completely wireless so as to remove percutaneous connections and the associated infection risks. However, wireless communication consumes significant power and there are strict heating limits in cortical tissue. Most iBMIs use Multi Unit Activity (MUA) processing, however the required bandwidth can be excessive for large channel counts in mm or sub-mm scale implants. As such, some form of data compression for MUA iBMIs is desirable.
September 2022
Selecting an effective amplitude threshold for neural spike detection
Zheng Zhang; Timothy G. Constandinou
This paper assesses and challenges whether commonly used methods for defining amplitude thresholds for spike detection are optimal. This is achieved through empirical testing of single amplitude thresholds across multiple recordings of varying SNR levels. Our results suggest that the most widely used noise-statistics-driven threshold can suffer from parameter deviation in different noise levels. The spike-noise-driven threshold can be an ideal approach to set the threshold for spike detection, which suffers less from the parameter deviation and is robust to sub-optimal settings.
September 2022
Tunable Fine-grained Clock Phase-shifting for FPGAs
Bardia Babaei; Dirk Koch
High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.
August 2022
An FPGA-based system for generalised electron devices testing
Patrick Foster, Jinqi Huang, Alex Serb, Spyros Stathopoulos, Christos Papavassiliou & Themis Prodromakis
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and 2× banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain 170pA current noise floor, 40ns pulse delivery at ±13.5V and 12mA maximum current drive/channel. We then showcase the instrument’s use in performing a selection of three characteristic measurement tasks: (a) current–voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.
August 2022
Memristor-assisted Background Calibration for Analog-to-Digital Converter
Zhaoguang Si; Chaohan Wang; Adil Malik; Shiwei Wang; Themis Prodromakis; Christos Papavassiliou
This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADC). A R-2R digital-to-analog converter (DAC) was implemented with a memristor array and other peripheral circuits. The background calibration detects the error caused by DAC mismatch and corrects it by adjusting the memristor’s memristance 1 in a feedback loop. The implemented circuit takes advantage of the memristor’s small area and multi-state switching property. Simulation results show the feasibility of using memristors to correct mismatch in high-resolution ADC design. The proposed system has been designed in a TSMC 180nm process. Memristors will be laid on the top of the chip via Metal 5 and Metal 6.
July 2022
Text Classification in Memristor-based Spiking Neural Networks
Jinqi Huang, Alex Serb, Spyros Stathopoulos, Themis Prodromakis
Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based spiking neural networks in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained spiking neural networks with memristor models: 1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or 2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches. This investigation further indicates that the simulation using statistic memristor models in the two approaches presented by this paper can assist the exploration of memristor-based SNNs in natural language processing tasks.
July 2022
An Absorbing Markov Chain Model for Stochastic Memristive Devices
Adil Malik; Christos Papavassiliou; Spyros Stathopoulos
In this paper we elaborate and verify a data-driven modelling approach, pertaining to the stochastic trajectory of the memristance upon the application of pulses. Our proposed approach is to model the memristor’s behaviour as a time-homogeneous Markov chain. We introduce a simplified method that estimates the states and the state transition probabilities of the model from device measurements. We show that such a memristor model, generally corresponds to an absorbing Markov chain, the physical implications of which are also discussed. We apply this modelling methodology to real-world Pt/TiO2/Pt memristors and present results that validate its effectiveness in capturing the stochastic features of these devices over various timescales.
July 2022
A tool for emulating neuromorphic architectures with memristive models and devices
Jinqi Huang, Spyros Stathopoulos, Alex Serb, and Themis Prodromakis
Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware
accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of
neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.
June 2022
Palimpsest memories stored in memristive synapses
Christos Giotis; Alexander Serb; Vasileios Manouras; Spyros Stathopoulos; Themis Prodromakis
Biological synapses store multiple memories on top of each other in a palimpsest fashion and at different time scales. Palimpsest consolidation is facilitated by the interaction of hidden biochemical processes governing synaptic efficacy during varying lifetimes. This arrangement allows idle memories to be temporarily overwritten without being forgotten, while previously unseen memories are used in the short term. While embedded artificial intelligence can greatly benefit from this functionality, a practical demonstration in hardware is missing. Here, we show how the intrinsic properties of metal-oxide volatile memristors emulate the processes supporting biological palimpsest consolidation. Our memristive synapses exhibit an expanded doubled capacity and protect a consolidated memory while up to hundreds of uncorrelated short-term memories temporarily overwrite it, without requiring specialized instructions. We further demonstrate this technology in the context of visual working memory. This showcases how emerging memory technologies can efficiently expand the capabilities of artificial intelligence hardware toward more generalized learning memories.
June 2022
An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).
June 2022
Measured behaviour of a memristor-based tuneable instrumentation amplifier
Fan Yang, Alexander Serb, Themis Prodromakis
A memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.
May 2022
An Open-Source RRAM Compiler
Dimitris Antoniadis, Andrea Mifsud, Peilong Feng, Timothy G. Constandinou
Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.
May 2022
A CMOS-based Characterisation Platform for Emerging RRAM Technologies
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G Constandinou
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device's resistance range to be between 1k and 10M with a minimum voltage range of 1.5V on the device.
May 2022
Impact of Zr top electrode on tantalum oxide-based electrochemical metallization resistive switching memory: towards synaptic functionalities
Niloufar Raeis-Hosseini, Shaochuan Chen, Christos Papavassiliou, Ilia Valov
Electrochemical metallization memory (ECM) devices have been made by sub-stoichiometric deposition of a tantalum oxide switching film (Ta2O5−x) using sputtering. We investigated the influence of zirconium as the active top electrode material in the lithographically fabricated ECM devices. A simple capacitor like (Pt/Zr/Ta2O5−x/Pt) structure represented the resistive switching memory. A cyclic voltammetry measurement demonstrated the electrochemical process of the memory device. The I–V characteristics of ECMs show stable bipolar resistive switching properties with reliable endurance and retention. The resistive switching mechanism results from the formation and rupture of a conductive filament characteristic of ECM. Our results suggest that Zr can be considered a potential active electrode in the ECMs for the next generation of nonvolatile nanoelectronics. We successfully showed that the ECM device can work under AC pulses to emulate the essential characteristics of an artificial synapse by further improvements.
April 2022
Advances in Organic and Perovskite Photovoltaics Enabling a Greener Internet of Things
Julianna Panidi, Dimitra G. Georgiadou, Theresa Schoetz, Themis Prodromakis
Organic and perovskite solar cells (PSCs) have made significant strides in the last couple of years achieving high power conversion efficiencies (18% and 29%, respectively) and exceptional stability. Ultra-flexible and environmentally stable organic and PSCs can effectively operate under various illumination settings. Herein, novel device concepts that comprise photovoltaic cells alone or in tandem with batteries or supercapacitors, acting as the main power supply to another microelectronic component, enabling self-powered electronics for the Internet of Things (IoT) are reviewed. Emphasis is placed on the specific requirements posed by such applications to pave the way to large scale commercialization. The importance of supporting a greener IoT ecosystem by eliminating toxic materials and solvents in the device fabrication process is highlighted.
April 2022
Selectively biased tri-terminal vertically-integrated memristor configuration
Vasileios Manouras, Spyros Stathopoulos, Alex Serb, Themis Prodromakis
Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.
March 2022
Formation of a ternary oxide barrier layer and its role in switching characteristic of ZnO-based conductive bridge random access memory devices
Firman Mangasa Simanjuntak, Julianna Panidi, Fayzah Talbi, Adam Kerrigan, Vlado K. Lazarov, and Themistoklis Prodromakis
The insertion of a metal layer between an active electrode and a switching layer leads to the formation of a ternary oxide at the interface. The properties of this self-formed oxide are found to be dependent on the Gibbs free energy of oxide formation of the metal (Δ𝐺∘𝑓). We investigated the role of various ternary oxides in the switching behavior of conductive bridge random access memory (CBRAM) devices. The ternary oxide acts as a barrier layer that can limit the mobility of metal cations in the cell, promoting stable switching. However, too low (higher negative value) Δ𝐺∘𝑓 leads to severe trade-offs; the devices require high operation current and voltages to exhibit switching behavior and low memory window (on/off) ratio. We propose that choosing a metal layer having appropriate Δ𝐺∘𝑓 is crucial in achieving reliable CBRAM devices.
February 2022
Algorithm and hardware considerations for real-time neural signal on-implant processing
Zheng Zhang, Oscar W Savolainen, Timothy G Constandinou
Various on-workstation neural-spike-based brain machine interface (BMI) systems have reached the point of in-human trials, but on-node and on-implant BMI systems are still under exploration. Such systems are constrained by the area and battery. Researchers should consider the algorithm complexity, available resources, power budgets, CMOS technologies, and the choice of platforms when designing BMI systems. However, the effect of these factors is currently still unclear.Approaches.Here we have proposed a novel real-time 128 channel spike detection algorithm and optimised it on microcontroller (MCU) and field programmable gate array (FPGA) platforms towards consuming minimal power and memory/resources. It is presented as a use case to explore the different considerations in system design.Main results.The proposed spike detection algorithm achieved over 97% sensitivity and a smaller than 3% false detection rate. The MCU implementation occupies less than 3 KB RAM and consumes 31.5 µW ch-1. The FPGA platform only occupies 299 logic cells and 3 KB RAM for 128 channels and consumes 0.04 µW ch-1.Significance.On the spike detection algorithm front, we have eliminated the processing bottleneck by reducing the dynamic power consumption to lower than the hardware static power, without sacrificing detection performance. More importantly, we have explored the considerations in algorithm and hardware design with respect to scalability, portability, and costs. These findings can facilitate and guide the future development of real-time on-implant neural signal processing platforms.
February 2022
NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing
Jinqi Huang, Spyros Stathopoulos, Alex Serb, Themis Prodromakis
Emerging two terminal nanoscale memory devices, known as memristors, have over the past decade demonstrated great potential for implementing energy efficient neuro-inspired computing architectures. As a result, a wide-range of technologies have been developed that in turn are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors' attributes in novel neuro-inspired topologies. In this paper, we present NeuroPack, a modular, algorithm level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to chose from a variety of neuron models, learning rules and memristors models. Its hierarchical structure, empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameters options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.
February 2022
How to Shrink My FPGAs—Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics
King Lok Chung, Nguyen Dao, Jing Yu, Dirk Koch
Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (= speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity.
February 2022
The Future of FPGA Acceleration in Datacenters and the Cloud
Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds.
January 2022
Thermal Effects on Initial Volatile Response and Relaxation Dynamics of Resistive RAM Devices
Thomas Abbey, Chris Giotis, Alex Serb, Spyros Stathopoulos, Themis Prodromakis
Resistive RAM (RRAM) or memristors are a class of electronic device whose resistance depends on voltage history. The changes in resistance can be divided into two categories, volatile and non-volatile. To date, the characteristics of non-volatile switching have been explored extensively with volatile switching behaviour still remaining more obscure. Here we investigate the temperature effects on TiOx based memristor volatility, and integrate these observations into a previously developed model for volatile switching. We show how device temperature affects the magnitude of the volatile resistive state in response to input stimulation, as well as the corresponding relaxation time constant. Importantly, these effects are polarity dependent. This work is part of an effort towards building a more comprehensive model of RRAM behaviour covering volatile and non-volatile phenomena as well as various environmental effects on them.
January 2022
A Stochastic Compact Model Describing Memristor Plasticity and Volatility
Adil Malik; Christos Papavassiliou; Spyros Stathopoulos
A memristor compact model, which can both capture state volatility and describe short-term and long-term memory transitions, is introduced. The model is based on an energy landscape acting as a pseudo-potential which generates the driving forces for configurational changes. A stable conductance change in this model is implemented through a sequence of transitions between states of plasticity occurring over different time-scales. Such transitions also modify the detail of the pseudopotential landscape, this way altering the probability distribution of subsequent state-change events. This approach departs from the usual method of applying perfectly non-volatile increments on the state variable. The model has been coded in Verilog-A, so that it can be used in many popular SPICE engines. The proposed model is semi-quantitatively fitted to measurements taken on Pt/TiO2/Pt stack memristor devices.
January 2022
Design of a Multi-State Memristive Memory
Chaohan Wang; Lijie Xie; Xiongfei Jiang; Ruixin Ge; Christos Papavassiliou
This paper presents an integrated memristive memory (RRAM) capable of storing 4 states in each memory location. RRAM advantages include non-volatility, low power consumption, high speed, and compatibility with existing CMOS technology. More importantly, RRAM has the potential to achieve multi-state storage on a single memory cell. Nevertheless, there is no multi-state RRAM integrated with CMOS technology that has been reported in literature. In this work, we propose a precise write-in and readout circuit for multi-state memristive memory. The memory is designed over a crossbar array architecture, a 1 transistor 1 memristor (1T1R) topology is employed to eliminate sneak-path currents. Data readout is carried out by two amplifiers and a 12-bit successive approximation analog to digital converter (SAR ADC). The RRAM successfully writes and reads 2-bit information by dividing the resistance of the memristor (memristance) into 4 states of 28kΩ±2kΩ(11),37kΩ±3kΩ(10),46kΩ±4kΩ(01) , and 56kΩ±4kΩ(00) . The total area of the proposed RRAM is 0.92 mm 2 . The RRAM is prepared to be made in TSMC 0.18μm process.
January 2022
Electron Transporting Perylene Diimide-Based Random Terpolymers with Variable Co-Monomer Feed Ratio: A Route to All-Polymer-Based Photodiodes
Stefania Aivali, Peisen Yuan, Julianna Panidi, Dimitra G. Georgiadou, Themis Prodromakis, Joannis K. Kallitsis, Panagiotis E. Keivanidis, and Aikaterini K. Andreopoulou
A route toward processable n-type terpolymers is presented herein based on the random donor–acceptor–donor–acceptor (D–A1)-(D–A2) molecular configuration. Carbazole is utilized as the electron donating unit (D) combined with perylene diimide (PDI) as the first electron acceptor (A1) and either one of two different benzothiadiazole (BTZ) derivatives (di-thienyl substituted-BTZ and di-3,4-ethylenedioxythienyl substituted-BTZ) as the second electron accepting unit (A2). Increasing the content of the PDI co-monomer resulted in terpolymers of higher molecular weights, enhanced solubility, and stronger n-type character. The physicochemical properties of the random PDI-Cz-BTZ derivatives are fine-tuned based on the feed ratio of the co-monomers. Photodiode devices were demonstrated, having photoactive layers composed of the rich in PDI terpolymer, namely, P4 having a 75% PDI content, and the PCE10 electron donor, under various ratios. For a range of P4 blend compositions, UV–Vis, is spectroscopy confirmed the strong absorption of the blend films across the 350–800 nm spectral region, and AFM imaging verified their low surface roughness. The study of the electro-optical device properties identified the 1:2 blending ratio as the optimum PCE10:P4 combination for maximum charge photogeneration efficiency. Despite the relatively deep LUMO energy of the n-type P4 terpolymer (ELUMO = −4.04 eV), trap-induced charge recombination losses were found to limit the PCE10:P4 photodiode performance. Unipolar devices of the P4-alone exhibited hole and electron mobility values of 2.2 × 10–4 and 6.3 × 10–5 cm2 V–1 s–1, respectively.
December 2021
Conduction channel configuration controlled digital and analog response in TiO 2 -based inorganic memristive artificial synapses
Firman Mangasa Simanjuntak, Chun-Ling Hsu, Thomas Abbey, Lung-Yu Chang, Sailesh Rajasekaran, Themis Prodromakis, Tseung-Yuen Tseng
The operating current regime is found to play a key role in determining the synaptic characteristic of memristor devices. A conduction channel that is formed using high current compliance prior to the synaptic operation results in digital behavior; the high current stimulus forms a complete conductive filament connecting the cathode and anode, and the high electric field promotes abrupt redox reactions during potentiation and depression pulsing schemes. Conversely, the conduction can be reconfigured to produce a filamentary-homogeneous hybrid channel by utilizing the low current stimulus, and this configuration enables the occurrence of analog behavior. The capabilities of memristors showing programmable digital-to-analog or analog-to-digital transformation open a wide range of applications in electronics. We propose a conduction mechanism to explain this phenomenon.
November 2021
Distributed neural interfaces: challenges and trends in scaling implantable technology
Katarzyna M Szostak, Peilong Feng, Federico Mazza, Timothy G Constandinou
Current implantable neural interfaces, both clinically available solutions and research tools, rely on a limited number of implanted devices (from one to few units). This factor, aside from the obvious spatial resolution limitations, does not conform to the paradigm of the brain as a massively parallel computational system and creates a bottleneck in the amount of information that could be exchanged between the brain and an external processing unit. This issue has fuelled recent research efforts towards the study of distributed neural interfaces, systems that depend on a network of implanted nodes. Such configuration allows to spread of the overall complexity across multiple devices, which can now be more easily scaled down in size and individual power consumption, improving their conformity with the surrounding tissue, which is a major concern in current monolithic solutions. However, this architecture brings a new set of challenges ranging from the optimization of ultra-low-power electronics, through the formulation of a wireless transmission scheme for efficient power delivery and data transfer to the investigation of novel materials and methods for the fabrication of micro-scale, long-term reliable implants. This chapter outlines state of the art and describes design considerations for the future autonomous, wireless distributed neural implants. Aspects of miniaturization and chronic stability of devices including materials choice, implantation procedure, packaging strategies and microelectrode types are described, alongside a discussion on different modalities to achieve wireless power transfer and data telemetry.
November 2021
Design Flow for Hybrid CMOS/Memristor Systems-Part I: Modeling and Verification Steps
Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis
Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
November 2021
Design Flow for Hybrid CMOS/Memristor Systems—Part II: Circuit Schematics and Layout
Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis
The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
October 2021
Technology agnostic frequency characterization methodology for memristors
Vasileios Manouras, Spyros Stathopoulos, Alex Serb & Themis Prodromakis
Over the past decade, memristors have been extensively studied for a number of applications, almost exclusively with DC characterization techniques. Studies of memristors in AC circuits are sparse, with only a few examples found in the literature, and characterization methods with an AC input are also sparingly used. However, publications concerning the usage of memristors in this working regime are currently on the rise. Here we propose a "technology agnostic" methodology for memristor testing in certain frequency bands. A measurement process is initially proposed, with specific instructions on sample preparation, followed by an equipment calibration and measurement protocol. This article is structured in a way which aims to facilitate the usage of any available measurement equipment and it can be applied on any type of memristive technology. The second half of this work is centered around the representation of data received from following this process. Bode plot and Nyquist plot representations are considered and the information received from them is evaluated. Finally, examples of expected behaviors are given, characterizing simulated scenarios which represent different internal device models and different switching behaviors, such as capacitive or inductive switching. This study aims at providing a cohesive way for memristor characterization, to be used as a good starting point for frequency applications, and for understanding physical processes inside the devices, by streamlining the measuring process and providing a frame in which data representation and comparison will be facilitated.
October 2021
The FABulous Open eFPGA Ecosystem in Action-From Specifications to Chips to Running Bitsteams
Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch
This demonstration shows the steps a designer has to take to specify and implement a chip with an embedded FPGA (eFPGA) using the FABulous open-source toolchain. We also show how the architecture graph is automatically generated for the open-source FPGA CAD tools (Yosys, ABC, nextpnr) to compile Verilog all the way to a bitstream. Ultimately, we demonstrate such bitstreams running on our FlexBex chip, which integrates an Ibex RISC-V core from lowRISC together with a FABulous eFPGA. The system supports multiple partially reconfigurable regions for hosting reconfigurable instruction set extensions, and the fabric provides logic, DSP, and memory slices.
September 2021
Open-source memory compiler for automatic RRAM generation and verification
Dimitrios Antoniadis, Peilong Feng, Andrea Mifsud, Timothy G Constandinou
The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility.
August 2021
Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOₓ-Based Memristors—Part I: Behavioral Model
Dhirendra Vaidya; Shraddha Kothari; Thomas Abbey; Ali Khiat; Spyros Stathopoulos; Loukas Michalas; Alexantrou Serb; Themistoklis Prodromakis
Memristor is a promising device as a fundamental building block for future unconventional system architectures such as neuromorphic computing, reconfigurable logic, and multibit memories. Therefore, to facilitate circuit design using memristors, accurate and efficient models spanning a wide range of programming voltages and temperatures are required. In the first part of this series, we propose a behavioral model for temperature dependence of nonvolatile switching dynamics of TiO x memristors. We begin by describing pulsed resistance transients (PRTs) of the memristors and then we use a multistage methodology to establish bias and temperature dependence of the model parameters. The proposed model is then shown to accurately describe the PRT characteristics of Pt/TiO x /Au and Pt/TiO x /Pt memristors.
August 2021
Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOₓ Memristors—Part II: Physics-Based Model
Dhirendra Vaidya; Shraddha Kothari; Thomas Abbey; Spyros Stathopoulos; Loukas Michalas; Alexantrou Serb; Themistoklis Prodromakis
In the second part of this series, we propose a physics-based model for describing the temperature dependence of TiO x -based memristors, both switching and static. We show that the current–voltage ( I – V ) characteristics of memristor in the nonswitching regime, indicating a Schottky emission mechanism, can be described by minor modifications to the Schottky current equation. This leads to a physics-based static I – V compact model. Simultaneously, we show that the temperature dependence of the switching dynamics model parameters naturally emerges as a mere scaling factor from the static I – V model. This is a computationally efficient approach, which does not require any additional parameters to extend the switching dynamics model for incorporating thermal dependence.
July 2021
Analogue front-end design for neural recording
Michal Maslik, Lieuwe B Leene, Timothy G Constandinou
There exist a number of key challenges in designing analogue front-end (AFE) recording systems to observe neural activity. These include a limited signal-to-noise ratio (SNR) of the neural biopotential signal itself, microvolt-level amplitudes, relatively low frequency signals and bandwidth, non-ideal electrochemical electrode properties resulting in added noise, DC drift, etc. Furthermore, there is a drive towards high channel count (and high density) systems incorporating hundreds or thousands of channels. The instrumentation in each channel needs to achieve low noise amplification, signal conditioning and digitisation with a minimal power consumption while achieving high noise efficiency and rejecting the sub-Hz electrode offset potential without the use of external passive components. Therefore, such systems should ideally be a fully integrated single-chip solution.
June 2021
A robust and automated algorithm that uses single-channel spike sorting to label multi-channel Neuropixels data
Zheng Zhang, Timothy G. Constandinou
This paper describes preliminary work towards an automated algorithm for labelling Neuropixel data that exploits the fact that adjacent recording sites are spatially oversampled. This is achieved by combining classical single channel spike sorting with spatial spike grouping, resulting in an improvement in both accuracy and robustness. This is additionally complemented by an automated method for channel selection that determines which channels contain high quality data. The algorithm has been applied to a freely accessible dataset, produced by Cortex Lab, UCL. This has been evaluated to have a accuracy of over 77% compared to a manually curated ground truth.
May 2021
Frequency Response of Metal-Oxide Memristors
Vasileios Manouras; Spyros Stathopoulos; Suresh Kumar Garlapati; Alex Serb; Themis Prodromakis
Memristors have been at the forefront of nanoelectronics research for the last few decades, offering a valuable component to reconfigurable computing. Their attributes have been studied extensively along with applications that leverage their state-dependent programmability in a static fashion. However, practical applications of memristor-based alternating current (ac) circuits have been rather sparse, with only a few examples found in the literature where their use is emulated at higher frequencies. In this work, we study the behavior of metal-oxide memristors under a noninvasive ac perturbation in a range of frequencies, from 10 3 to 10 7 Hz. Metal-oxide memristors are found to behave as RC low-pass filters and they present a variable cut-off frequency when their state is switched, thus providing a window of reconfigurability when used as filters. We further study this behavior across distinct material systems, and we show that the usable reconfigurability window of the devices can be tailored to encompass specific frequency ranges by amending the devices' capacitance. This study extends current knowledge on metal-oxide memristors by characterizing their frequency-dependent characteristics, providing useful insights for their use in reconfigurable ac circuits.
May 2021
FlexBex: A Framework for RISC-V and Embedded FPGA Hybrids for Reconfigurable Instruction Extension
Nguyen Dao and Dirk Koch
This paper presents an all open-source framework for adding embedded FPGAs into RISC-V CPUs. In our approach, an eFPGA is directly coupled with the CPU, and through supporting partial reconfiguration, instructions can be swapped at runtime. The eFPGA fabric is tiled into multiple slots in order to host different instructions in parallel, and multiple slots can be combined for hosting more complex instructions. Instructions can be swapped without interrupting the CPU, and instructions can have a different number of execution cycles to provide more flexibility for instruction implementations. Our case study integrates an Ibex RISC-V core from lowRISC together with our custom embedded FPGA supporting multiple regions, with logic, DSP, and Register File slices. This system had been taped out in a 180um TSMC process.
April 2021
Autonomous wireless system for robust and efficient inductive power transmission to multi-node implants
P Feng, TG Constandinou
A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed ‘swarm’ of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network.
April 2021
Negative effect of cations out-diffusion and auto-doping on switching mechanisms of transparent memristor devices employing ZnO/ITO heterostructure
Firman Mangasa Simanjuntak, Sridhar Chandrasekaran, Debashis Panda, Sailesh Rajasekaran, Cut Rullyani, Govindasamy Madhaiyan, Themistoklis Prodromakis, Tseung-Yuen Tseng
An excessive unintentional out-diffused In atom into the switching layer is a potential threat to the switching stability of memristor devices having indium tin oxide (ITO) as the electrode. We suggest that the physical factor (bombardment of Ar ions and bombardment-induced localized heat during ZnO deposition) and chemical factor (bonding dissociation energy, point defects, and bond length of atoms) are responsible for promoting the out-diffusion. The In atom acts as dopant in the ZnO lattice that degenerates the ZnO insulative behavior. Furthermore, the In ions take part in the conduction mechanism where they may compete with other mobile species to form and rupture the filament, and hence, deteriorate the switching performance. We propose a facile UV/O3 (UVO) treatment to mitigate such damaging effects.
April 2021
Memristor-Based Pass Gate for FPGA Programmable Routing Switch
Dirk Kock and Nguyen Dao
The advancement of memristor technologies has recently attracted huge interest in exploiting their superior potential properties for enabling hybrid memristor-CMOS systems. This work presents a memristor-based Pass Gate - mPG, as a primitive cell as well as its deployment for implementing programmable routing switches targeting FPGAs. The mPG, consists of a transistor and output buffer(s) and can be used to discriminate resistance states for both binary and multi-state memristor technologies without additional circuitry. The proposed routing structure eliminates leakage current and avoids degrading memristor’s characteristics due to voltage drops, which are essential factors for building reliable large-scale digital systems like FPGAs. Simulation results of mPG-based switches show that the gate can be deployed for a wide range of memristor resistance with a switching delay in the subnanosecond range
April 2021
Accounting for Memristor I-V Non-Linearity in Low Power Memristive Amplifiers
Jiaqi Wang; Alexander Serb; Christos Papavassiliou; Themistoklis Prodromakis
Detecting neuronal activity for rehabilitation/assistive devices is an example of extreme edge computing, featuring stringent requirements for data bandwidth from implantable acquisition system, low-power consumption and ideally also low latency. Recently, we proposed a neural recording system which detects neural spikes directly on the signals collected from electrophysiological probes. The system achieves power efficiency by utilising a combination of integrative sensing and ultra-fine offset compensation. A central component of this design is a memristive load, which is utilised as a trimming device along the differential branches of the core amplifier, ultimately allowing system offset tuning with μν precision. Previous work has assumed that the memristive device features a linear, or nearly-linear current-voltage (IV) characteristic. In this paper, we study the impact of memristor IV non-linearity on the effective gain and offset compensation capability of the system. Results show that the non-linearity experimentally measured from our in-house metal-oxide memristor technology only induces a small gap between nominal resistive state and static RS (as reflected on the IV). This leads to a very small degradation of gain (≈ 2.5%) and offset compensation (≈ 50% increased offset tuning sensitivity), but very crucially proves that introducing IV non-linearity does not materially change either the extreme offset trimming precision or the overall performance. This was the last conceptual bottleneck identified before practical implementation and it has now been overcome.
April 2021
An Adiabatic Regenerative Capacitive Artificial Neuron
Sachin Maheshwari; Alexander Serb; Christos Papavassiliou; Themistoklis Prodromakis
In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1 MHz indicates a æ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a æ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.
April 2021
Low-power electronic technologies for harsh radiation environments
Jeffrey Prinzie, Firman Mangasa Simanjuntak, Paul Leroux & Themis Prodromakis
Electronic technologies that can operate in harsh radiation environments are important in space, nuclear and avionic applications. However, radiation-hardened (rad-hard) integrated circuits often require additional processing and more complex configurations than conventional systems. Here we review the development of low-power, rad-hard electronics, examining the underlying phenomena of radiation-induced electronic failure and the design methodologies available with conventional complementary metal–oxide–semiconductor (CMOS) technologies to mitigate the problem. We also explore the potential use and applications of various emerging memory technologies in rad-hard electronics.
April 2021
Adaptive spike detection and hardware optimization towards autonomous, high-channel-count BMIs
Zheng Zhang , Timothy G Constandinou
Background: The progress in microtechnology has enabled an exponential trend in the number of neurons that can be simultaneously recorded. The data bandwidth requirement is however increasing with channel count. The vast majority of experimental work involving electrophysiology stores the raw data and then processes this offline; to detect the underlying spike events. Emerging applications however require new methods for local, real-time processing.

New methods: We have developed an adaptive, low complexity spike detection algorithm that combines three novel components for: (1) removing the local field potentials; (2) enhancing the signal-to-noise ratio; and (3) computing an adaptive threshold. The proposed algorithm has been optimised for hardware implementation (i.e. minimising computations, translating to a fixed-point implementation), and demonstrated on low-power embedded targets.

Main results: The algorithm has been validated on both synthetic datasets and real recordings yielding a detection sensitivity of up to 90%. The initial hardware implementation using an off-the-shelf embedded platform demonstrated a memory requirement of less than 0.1 kb ROM and 3 kb program flash, consuming an average power of 130 μW.

Comparison with existing methods: The method presented has the advantages over other approaches, that it allows spike events to be robustly detected in real-time from neural activity in a completely autonomous way, without the need for any calibration, and can be implemented with low hardware resources.

Conclusion: The proposed method can detect spikes effectively and adaptively. It alleviates the need for re-calibration, which is critical towards achieving a viable BMI, and more so with future 'high bandwidth' systems' targeting 1000s of channels.
March 2021
Transformation of digital to analog switching in TaOx-based memristor device for neuromorphic applications
Aftab Saleem, Firman Mangasa Simanjuntak, Sridhar Chandrasekaran, Sailesh Rajasekaran, Tseung-Yuen Tseng, Themis Prodromakis
An oxidizable metal diffusion barrier inserted between the active metal electrode and the switching layer decreases the electroforming voltage and enhances the switching stability and synaptic performances in TaOx-based conducting bridge memristor devices. The TiW barrier layer avoids an excessive metal ion diffusion into the switching layer, while the TiWOx interfacial layer is formed between the barrier and the switching layer. It modulates the oxygen vacancy distribution at the top interface and contributes to the formation and rupture of the metal ion-oxygen vacancy hybrid conducting bridge. We observe that the device that relies upon non-hybrid (metal ions only) conducting bridge suffers from poor analogous performance. Meanwhile, the device made with the barrier layer is capable of providing 2-bit memory and robust 50 stable epochs. TaOx also acts as resistance for suppressing and a thermal enhancement layer, which helps to minimize overshooting current. The enhanced analog device with high linear weight update shows multilevel cell characteristics and stable 50 epochs. To validate the neuromorphic characteristic of the devices, a simulated neural network of 100 synapses is used to recognize 10 × 10 pixel images.
February 2021
FABulous: an Embedded FPGA
Nguyen Dao and Dirk Koch
At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source FPGA framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as FPGA CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded FPGA fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node.
January 2021
Memristor-based Pass Gate Targeting for FPGA Look-Up Table
Nguyen Dao and Dirk Koch
This work proposes a memristor-based Pass Gate - mPG, as a primitive cell for translating memristor resistance states into logic targeting for FPGA Look-Up Tables (LUTs). The mPG consists of a pass transistor with buffers, and it can work with both binary and multibit memristors. The utilization of mPGs for the configuration bit storage in a new LUT architecture based on multibit memristors is introduced. Unlike other prior structures, the proposed architecture not only eliminates leakage current and extra sense amplifier/comparator circuitry but also prevents degrading memristor's characteristics; thus, more reliable systems can be developed. Simulation results show that the gate can be deployed for a wide range of memristor's resistance with a switching delay in the nanosecond range. Physical implementations of multibit memristor-based LUTs demonstrate that up to 80% of the design area and/or the number of transistors could be saved in comparison to standard SRAM-based designs. Furthermore, mPG-based design considerations are thoroughly analyzed and presented.
December 2020
FlexBex: A RISC-V with a Reconfigurable Instruction Extension
Nguyen Dao; Andrew Attwood; Bea Healy; Dirk Koch
This paper presents an all open-source framework for adding embedded FPGAs into RISC-V CPUs. In our approach, an eFPGA is directly coupled with the CPU, and through supporting partial reconfiguration, instructions can be swapped at runtime. The eFPGA fabric is tiled into multiple slots in order to host different instructions in parallel, and multiple slots can be combined for hosting more complex instructions. Instructions can be swapped without interrupting the CPU, and instructions can have a different number of execution cycles to provide more flexibility for instruction implementations. Our case study integrates an Ibex RISC-V core from lowRISC together with our custom embedded FPGA supporting multiple regions, with logic, DSP, and Register File slices. This system had been taped out in a 180um TSMC process.
December 2020
UV induced resistive switching in hybrid polymer metal oxide memristors
Spyros Stathopoulos, Ioulia Tzouvadaki, Themis Prodromakis
There is an increasing interest for alternative ways to program memristive devices to arbitrary resistive levels. Among them, light-controlled programming approach, where optical input is used to improve or to promote the resistive switching, has drawn particular attention. Here, we present a straight-forward method to induce resistive switching to a memristive device, introducing a new version of a metal-oxide memristive architecture coupled with a UV-sensitive hybrid top electrode obtained through direct surface treatment with PEDOT:PSS of an established resistive random access memory platform. UV-illumination ultimately results to resistive switching, without involving any additional stimulation, and a relation between the switching magnitude and the applied wavelength is depicted. Overall, the system and method presented showcase a promising proof-of-concept for granting an exclusively light-triggered resistive switching to memristive devices irrespectively of the structure and materials comprising their main core, and, in perspective can be considered for functional integrations optical-induced sensing.
December 2020
UV Induced Resistive Switching in Hybrid Polymer Metal Oxide Memristors
Spyros Stathopoulos, Ioulia Tzouvadaki & Themis Prodromakis
There is an increasing interest for alternative ways to program memristive devices to arbitrary resistive levels. Among them, light-controlled programming approach, where optical input is used to improve or to promote the resistive switching, has drawn particular attention. Here, we present a straight-forward method to induce resistive switching to a memristive device, introducing a new version of a metal-oxide memristive architecture coupled with a UV-sensitive hybrid top electrode obtained through direct surface treatment with PEDOT:PSS of an established resistive random access memory platform. UV-illumination ultimately results to resistive switching, without involving any additional stimulation, and a relation between the switching magnitude and the applied wavelength is depicted. Overall, the system and method presented showcase a promising proof-of-concept for granting an exclusively light-triggered resistive switching to memristive devices irrespectively of the structure and materials comprising their main core, and, in perspective can be considered for functional integrations optical-induced sensing.
October 2020
Bidirectional Volatile Signatures of Metal-Oxide Memristors-Part II: Modeling
C. Giotis; A. Serb; S. Stathopoulos; T. Prodromakis
Volatility in metal-oxide resistive random access memory (RRAM) families has mostly been treated as an unwanted side-effect, although recently there are trends to interpret such behavior as an additional technological feature. To date, the field has seen early demonstrations of possible applications that harness volatility. Moreover, some work has been conducted to understand both the mechanisms responsible for this behavior. In the context of modeling RRAM volatility, we still lack a comprehensive model that could allow simulations in a larger scale. In an attempt to fill this gap, this work presents a modeling framework that can account for RRAM relaxation characteristics. Specifically, we show how volatility can be simulated to significant accuracy when the resistive state (RS) of a device as well as the stimulus protocol in use are well-defined. Importantly, our approach is solely data-driven and decoupled from previous physical modeling studies on volatility. Our results work for both stimulation polarities and are consistent for a number of TiO x devices in use. Moreover, the mathematical relations that unfold via modeling volatility provide further intuition on the effect that invasive protocols can have on this technology. This modeling solution enables more advanced studying of memristive technologies in one hand, as well as more intricate designs of larger systems that can account for transient RRAM changes over time.
September 2020
A mixed-signal spatio-temporal signal classifier for on-sensor spike sorting
G.Haessig, D.Garcia-Lesta, G.Lenz, R.Benosman, P.Dudek
Neuromorphic systems provide an alternative to conventional computing hardware, promising low-power operation suitable for sensory-processing and edge computing. In this paper, we present a mixed-signal processing system designed to provide on-sensor classification of signals obtained from multielectrode array neural recordings. The designed circuits implement a real-time spike sorting algorithm, and operate on signals represented by asynchronous event streams. We combine analog circuits computation primitives (temporal surface generation, distance computation, winner-take-all) to implement a spatiotemporal clustering algorithm, classifying signals acquired by
neighbouring electrodes. The prototype chip has been submitted for fabrication in a 180nm CMOS technology. The circuits are designed to fit, alongside signal conditioning and conversion circuits, in the area under the recording electrodes (below 80x80um per electrode). Circuit implementation details and simulation results are presented. The expected neural spike recognition rates of 75% in a single-layer network and 88% in a 2-layer network are comparable with a software implementation, while the system is designed to provide a low-power embedded real-time solution.
This work provides a foundation towards the design of a large scale neuromorphic processing system, to be embedded in brainmachine interfaces.
September 2020
A Reconfigurable CMOS-Memristor Active Inductor
Jiawei Shen; Spyros Stathopoulos; Themis Prodromakis; Christos Papavassiliou
A methodology is introduced here to exploit the programmability of the memristors in order to realize reconfigurable monolithic analogue circuit elements. Classical network synthesis methods are used to synthesize adjustable active inductors with inductance values exceeding those of on-chip passives by several orders of magnitude. In this paper, a wide range of active inductance values are obtained by employing memristor to control the biasing current of operational transconductance amplifiers used to implement gyrators. The gyration constant of the proposed gyrator will be linearly controlled by memristance state. The implementation of the designed circuit is realized in 0.18μm commercially available complementary metal-oxide-semiconductor (CMOS) technology from TSMC. Circuit performance is simulated using Cadence Virtuoso. The utilized off-chip memristor is a metal-oxide bi-layer memristor which exhibits a non-volatile memristance range of 4.7kΩ to 170kΩ. The active inductance range achieved is from approximately 95μH to 1.55mH with an inductive bandwidth of 69MHz and 18MHz respectively. The total power consumption is between 0.21mW to 1.95mW depending on the memristance and equivalent inductance.
September 2020
An FPGA Based System for Interfacing with Crossbar Arrays
Patrick Foster; Jinqi Huang; Alex Serb; Themis Prodromakis; Christos Papavassiliou
Memristor crossbar arrays offer a novel new approach for designing high density non-volatile memory; however, precise measurement of resistive crossbar elements requires parallel current sensing capability not found in existing instruments. To provide this capability, we have designed and built an FPGA-based crossbar control instrument with independent per-channel biasing and measuring. In this paper, we cover the architecture of this new instrument, its operation and interface, and the results of testing conducted on the instruments pulse driver circuitry.
September 2020
Live Demonstration: Electroforming of TiO2–x Memristor Devices using High Speed Pulses
Patrick Foster; Jinqi Huang; Alex Serb; Themis Prodromakis; Christos Papavassiliou
In this demonstration, we present a new electro-forming process, along with a new instrument to support this procedure. Memristor arrays will be available for the user to electroform, write, and read the resulting resistive state of the devices.
September 2020
Monitoring PSA levels as chemical state-variables in metal-oxide memristors
Ioulia Tzouvadaki, Spyros Stathopoulos, Tom Abbey, Loukas Michalas, Themis Prodromakis
Medical interventions increasingly rely on biosensors that can provide reliable quantitative information. A longstanding bottleneck in realizing this, is various non-idealities that generate offsets and variable responses across sensors. Current mitigation strategies involve the calibration of sensors, performed in software or via auxiliary compensation circuitry thus constraining real-time operation and integration efforts. Here, we show that bio-functionalized metal-oxide memristors can be utilized for directly transducing biomarker concentration levels to discrete memory states. The introduced chemical state-variable is found to be dependent on
the devices’ initial resistance, with its response to chemical stimuli being more pronounced for higher resistive states. We leverage this attribute along with memristors’ inherent state programmability for calibrating a biosensing array to render a homogeneous response across all cells. Finally, we demonstrate the application of this technology in detecting Prostate Specific Antigen in clinically relevant levels (ng/ml), paving the way towards applications in large multi-panel assays.
September 2020
Bidirectional Volatile Signatures of Metal-Oxide Memristors--Part I: Characterization
Christos Giotis, Alex Serb, Spyros Stathopoulos, Loukas Michalas, Ali Khiat and Themis Prodromakis
The multistate capabilities as well as the intrinsic integrating properties of memristors deem them suitable candidates for the realization of novel neuromorphic applications. To date, much of their prestige arises mostly from the versatility that is promised by the nonvolatile device families. However, memristors also exhibit volatile characteristics, which for as long as they remain unknown, will hinder their integration to large-scale applications. In this article, we present a comprehensive study for characterizing the relaxation dynamics of TiOₓ resistive RAM (RRAM) devices within a predefined volatility framework. These dynamics are tightly linked to the total energy of stimulation, and device relaxation can be accurately described using simple mathematical models. Moreover, we show that RRAM volatility is bidirectional and that relaxation time constants heavily depend on the level of invasiveness caused by programming stimulation. Our work further includes a demonstration of how volatility can be characterized within a specific time window. Moreover, our protocol can be altered to fit the specific needs of potential applications. We anticipate that the universality of our method can act as a stepping stone toward the understanding and modeling of volatile memristors across different technologies and materials, enabling the realization of a new family of time-related applications.
August 2020
Suboxide interface induces digital-to-analog switching transformation in all Ti-based memristor devices
Chang L-Y, Simanjuntak FM, Hsu C-L, Chandrasekaran S, Tseng T-Y
Oxidation of TiN is a diffusion-limited process due to the high stability of the TiN metallic state at the TiN/TiO2 junction. Hence, the TiN/TiO2/TiN device being the inability to form a suitable interfacial layer results in the exhibition of abrupt current (conductance) rise and fall during the set (potentiation) and reset (depression) processes, respectively. Interfacial engineering by depositing Ti film served as the oxygen gettering material on top of the TiO2 layer induces a spontaneous reaction to form a TiOx interfacial layer (due to the low Gibbs free energy of suboxide formation). Such an interface layer acts as an oxygen reservoir that promotes gradual oxidation and reduction during the set and reset processes. Consequently, an excellent analog behavior having a 2-bit per cell and robust epoch training can be achieved. However, a thick interfacial layer may degrade the switching behavior of the device due to the high internal resistance. This work suggests that interfacial engineering could be considered in designing high-performance analog memristor devices.
August 2020
A Fast, Highly Flexible and Transparent TaOx-based Environmentally Robust Memristor for Wearable and Aerospace Application
Rajasekaran S, Simanjuntak FM, Panda D, Chandrasekarang S, Aluguri R, Saleem A, Tseng T-Y.
Memristor devices that can operate at high speed with high density and non-volatile capabilities have great potential for the development of high data storage and robust wearable devices. However, in real-time the performance of memristors are challenged by their instability towards harsh working conditions such as high temperature, extreme humidity, photo irradiation and mechanical bending. Herein, we introduce a TaOx/AlN based flexible and transparent memristor device having stable endurance under extreme 2 mm bending (for more than 107 cycles) with ON/OFF ratio of more than 2 orders of magnitude at 25 ns rapid switching. This device performs excellent flexibility under extreme bending conditions (bending radius of 2 mm) even with intense ultraviolet radiation. A thin AlN insertion layer having low dielectric and high thermal conductivity play a crucial role in improving the switching stability and device flexibility. In particular, the devices exhibit excellent minimum switching fluctuations under UV irradiations, 105 s nonvolatility retention at high temperature (135˚C), various gas ambient and, damp heat test (humidity 95.5%, 83˚C) due to the indium metal drift during switching process and high bonding energy of Ta-O. Most importantly, direct observation of indium metal strongly anchored in TaOx switching layer during switching process is reported for the first time via transmission electron microscopy which provides clear insights on the switching phenomenon. Furthermore, results of electrical and material analyses explain that our facile device design has excellent potential for wearable and aerospace applications.
August 2020
Fast, Highly Flexible, and Transparent TaO x -Based Environmentally Robust Memristors for Wearable and Aerospace Applications
Sailesh Rajasekaran, Firman Mangasa Simanjuntak, Debashis Panda, Sridhar Chandrasekaran, Rakesh Aluguri, Aftab Saleem, and Tseung-Yuen Tseng
Memristor devices that can operate at high speed with high density and nonvolatile capabilities have great potential for the development of high data storage and robust wearable devices. However, in real-time, the performance of memristors is challenged by their instability toward harsh working conditions such as high temperature, extreme humidity, photo irradiation, and mechanical bending. Herein, we introduce a TaOx/AlN-based flexible and transparent memristor device having stable endurance under extreme 2 mm bending (for more than 107 cycles) with an ON/OFF ratio of more than 2 orders of magnitude at 25 ns rapid switching. This device exhibits excellent flexibility under extreme bending conditions (bending radius of 2 mm) even with intense ultraviolet (UV) radiation. A thin AlN insertion layer having low dielectric and high thermal conductivity plays a crucial role in improving the switching stability and device flexibility. In particular, the devices exhibit excellent minimum switching fluctuations under UV irradiation, >106 s nonvolatility retention at high temperature (135 °C), various gas ambient, and damp heat test (humidity 95.5%, 83 °C) because of the indium metal drift during the switching process and high bonding energy of Ta–O. Most importantly, direct observation of indium metal strongly anchored in the TaOx switching layer during the switching process is reported for the first time via transmission electron microscopy, which provides clear insights into the switching phenomenon. Furthermore, the results of electrical and material analyses explain that our facile device design has excellent potential for wearable and aerospace applications.
April 2020
Memristor-Enabled Reconfigurable Integrated Circuits
Jakub Szypicyn, Christos Papavassiliou, Georgios Papandroulidakis, Geoff Merrett, Alex Serb, Spyros Stathopoulos, Themis Prodromakis
The holy grail of analogue integrated circuit design is adjustable analogue delay element. Of course, all analogue circuits are filters. Internal delays impose overall low-pass character to all circuits so that broadband amplifiers are lowpass filters, while high-pass amplifiers are in fact band-pass filters.
April 2020
Memristor-based Reconfigurable Circuits: Challenges in Implementation
Nguyen Cong Dao and Dirk Koch
The emergence of memristor technologies has recently received much attention due to their promising features, expecting to be a key driver in the post-CMOS era. With its ultra-low power, higher density capability and non-volatile characteristics, memristor technology is considered as the best candidate to replace SRAM cells or be employed for routing in digital reconfigurable systems. Although memristor-based reconfigurable circuits can offer many advantages over the conventional CMOS designs, limitations in the utilization of memristor technologies such as electroforming or programming structures have not been thoroughly considered and discussed. This work looks into recent trends in exploiting memristor technologies in reconfigurable circuits and then discusses implementation challenges like memristor programming, reliability and operation of memristor-based memory cells for digitally reconfigurable circuits.
April 2020
Memristor-Enabled Reconfigurable Integrated Circuits
Jakub Szypicyn; Christos Papavassiliou; Georgios Papandroulidakis; Geoff Merrett; Alex Serb; Spyros Stathopoulos; Themis Prodromakis
The holy grail of analogue integrated circuit design is adjustable analogue delay element. Of course, all analogue circuits are filters. Internal delays impose overall low-pass character to all circuits so that broadband amplifiers are lowpass filters, while high-pass amplifiers are in fact band-pass filters.
February 2020
Memristive synapses connect brain and silicon spiking neurons.
Alexantrou Serb, Andrea Corna, Richard George, Ali Khiat, Federico Rocchi, Marco Reato, Marta Maschietto, Christian Mayr, Giacomo Indiveri, Stefano Vassanelli, Themistoklis Prodromakis
Brain function relies on circuits of spiking neurons with synapses playing the key role of merging transmission with memory storage and processing. Electronics has made important advances to emulate neurons and synapses and brain-computer interfacing concepts that interlink brain and brain-inspired devices are beginning to materialise. We report on memristive links between brain and silicon spiking neurons that emulate transmission and plasticity properties of real synapses. A memristor paired with a metal-thin film titanium oxide microelectrode connects a silicon neuron to a neuron of the rat hippocampus. Memristive plasticity accounts for modulation of connection strength, while transmission is mediated by weighted stimuli through the thin film oxide leading to responses that resemble excitatory postsynaptic potentials. The reverse brain-to-silicon link is established through a microelectrode-memristor pair. On these bases, we demonstrate a three-neuron brain-silicon network where memristive synapses undergo long-term potentiation or depression driven by neuronal firing rates.
December 2019
A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing
A. Serb, I. Kobyzev, J. Wang and T. Prodromakis
One of the main, long-term objectives of artificial intelligence is the creation of thinking machines. To that end, substantial effort has been placed into designing cognitive systems; i.e. systems that can manipulate semantic-level information. A substantial part of that effort is oriented towards designing the mathematical machinery underlying cognition in a way that is very efficiently implementable in hardware. In this work, we propose a ‘semi-holographic’ representation system that can be implemented in hardware using only multiplexing and addition operations, thus avoiding the need for expensive multiplication. The resulting architecture can be readily constructed by recycling standard microprocessor elements and is capable of performing two key mathematical operations frequently used in cognition, superposition and binding, within a budget of below 6 pJ for 64-bit operands. Our proposed ‘cognitive processing unit’ is intended as just one (albeit crucial) part of much larger cognitive systems where artificial neural networks of all kinds and associative memories work in concord to give rise to intelligence.
December 2019
An Electrical Characterisation Methodology for Bench-marking Memristive Device Technologies
Spyros Stathopoulos, Loukas Michalas, Ali Khiat, Alexantrou Serb & Themis Prodromakis
The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies.
November 2019
Impact of Line Edge Roughness on ReRAM Uniformity and Scaling
Vassilios Constantoudis, George Papavieros, Panagiotis Karakolis, Ali Khiat, Themistoklis Prodromakis, and Panagiotis Dimitrakis
We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method.
July 2019
A Memristive Switching Uncertainty Model
Spyros Stathopoulos ; Alexantrou Serb ; Ali Khiat ; Maciej Ogorzałek ; Themis Prodromakis
In this paper, we endeavor to evaluate and model switching noise in resistive random access memory (RRAM) devices. Although noise is always present in physical systems, the sources of which can be attributed to many different effects, in this paper, we are focusing our attention on a specific type-switching noise. Using alternating pulse programming and read trains across different voltages, we acquire a large data set below and above the switching threshold and construct what we define as increment plots, ΔR versus R. Then, through a detailed statistical analysis, we quantify the localized uncertainty among consecutive points using a sliding window of up to N points accounting for any statistical artifacts that arise. By separating the data accumulated from programming and read-out and analyzing them individually, we can subtract a baseline noise floor from the overall switching uncertainty. In this way, we effectively decouple it from other noise sources that affect the device at rest. In the end, an F(R, V) surface can be extracted that closely follows the behavior of uncertainty of the device during programming. This modeled surface can be used as an approximation of the noise behavior of the device or it can be readily incorporated as an additional component to existing switching models.
June 2019
An electrical characterisation methodology for identifying the switching mechanism in TiO2 memristive stacks
L. Michalas, S. Stathopoulos, A. Khiat & T. Prodromakis
Resistive random access memories (RRAMs) can be programmed to discrete resistive levels on demand via voltage pulses with appropriate amplitude and widths. This tuneability enables the design of various emerging concepts, to name a few: neuromorphic applications and reconfigurable circuits. Despite the wide interest in RRAM technologies there is still room for improvement and the key lies with understanding better the underpinning mechanism responsible for resistive switching. This work presents a methodology that aids such efforts, by revealing the nature of the resistive switching through assessing the transport properties in the non-switching operation regimes, before and after switching occurs. Variation in the transport properties obtained by analysing the current-voltage characteristics at distinct temperatures provides experimental evidence for understanding the nature of the responsible mechanism. This study is performed on prototyped device stacks that possess common Au bottom electrodes, identical TiO2 active layers while employing three different top electrodes, Au, Ni and Pt. Our results support in all cases an interface controlled transport due to Schottky emission and suggest that the acquired gradual switching originates by the bias induced modification of the interfacial barrier. Throughout this study, the top electrode material was found to play a role in determining the electroforming requirements and thus indirectly the devices’ memristive characteristics whilst both the top and bottom metal/oxide interfaces are found to be modified as result of this process.
May 2019
A 3rd Order Time Domain Delta Sigma Modulator with Extended-Phase Detection
Lieuwe B Leene and Timothy G. Constandinou
This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feedforward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm 2 and consumes 13.7 μW of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.
May 2019
A 68μW 31kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR
Lieuwe B. Leene ; Shiva Letchumanan ; Timothy G. Constandinou
This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM S of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm 2 area requirement.
May 2019
An Analogue-Domain, Switch-Capacitor-Based Arithmetic-Logic Unit
Alexander Serb and Themis Prodromakis
The continuous maturation of novel nanoelectronic devices exhibiting finely tuneable resistive switching is rekindling interest in analogue-domain computation. Regardless of domain, a useful computational module is the arithmetic-logic unit (ALU), which is capable of performing one or more fundamental mathematical operations (typical example: addition and subtraction). In this work we report on a design for an analogue ALU (aALU) capable of performing barrel addition and subtraction (i.e. ADD/SUB in modular arithmetic). The circuit only requires 5 minimum-size transistors and 1 capacitor. We show that our aALU is in principle capable of handling 5 bits of information using a single input/output wire. Core power dissipation per operation is estimated to peak at ≈ 59 f J (input operand-dependent) in TSMC's 65 nm technology.
May 2019
A Digital In-Analogue Out Logic Gate Based on Metal-Oxide Memristor Devices
G. Papandroulidakis; L. Michalas; A. Serb; A. Khiat; Geoff V. Merrett; T. Prodromakis
An important cornerstone of data processing is the ability to efficiently capture structure in data and perform data classification. More recently, memristive technologies enabled the incorporation of continuous tuneable resistive elements directly in hardware, thus increasing the efficiency of reconfigurable systems power and area-wise. Memristors are a promising candidate for reconfigurable circuits capable of carrying out classification with physical computing, such as dot-product vector multiplication and accumulation technique. In this work, we demonstrate a novel proof-of-concept memristor-based Digital-In-Analogue-Out logic circuit and present preliminary results highlighting the effect of non-uniform non-linear memristor IV characteristics that result in device-to-device behavioural variation.
March 2019
Practical Implementation of Memristor-Based Threshold Logic Gates
Georgios Papandroulidakis; Alexander Serb; Ali Khiat; Geoff V. Merrett; Themis Prodromakis
Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing and benefits which follow from its technological attributes, such as nanoscale dimensions, low-power operation, and multi-state programming. At the same time, the design with CMOS is quickly reaching its physical and functional limitations, and further research toward novel logic families, such as threshold logic gates (TLGs), is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate two-input, three-input, and four-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing a promise as an alternative hardware-friendly implementation of artificial neural networks. Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used toward an in silico classifier.
December 2018
Challenges hindering memristive neuromorphic hardware from going mainstream
Gina C. Adam, Ali Khiat & Themis Prodromakis
Memristive devices have elicited intense research in the past decade thanks to their inherent low voltage operation, multi-bit storage and cost-effective manufacturability. Nonetheless, several outstanding performance and manufacturability challenges have prevented the widespread industry adoption of redox-based memristive matrices. Here, we discuss these challenges in terms of key metrics and propose a roadmap towards realizing competitive memristive-based neuromorphic processing systems.
December 2018
A Data-Driven Verilog-A ReRAM Model
Ioannis Messaris, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis, Themistoklis Prodromakis
The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
November 2018
Spike sorting using non-volatile metal-oxide memristors
Isha Gupta, Alexantrou Serb, Ali Khiat, Maria Trapatselia and Themistoklis Prodromakis
Electrophysiological techniques have improved substantially over the past years to the point that neuroprosthetics applications are becoming viable. This evolution has been fuelled by the advancement of implantable microelectrode technologies that have followed their own version of Moore’s scaling law. Similarly to electronics, however, excessive data-rates and strained power budgets require the development of more efficient computation paradigms for handling neural data in situ; in particular the computationally heavy task of events classification. Here, we demonstrate how the intrinsic analogue programmability of memristive devices can be exploited to perform spike-sorting on single devices. Leveraging the physical properties of nanoscale memristors allows us to demonstrate that these devices can capture enough information in neural signal for performing spike detection (shown previously) and spike sorting at no additional power cost.
October 2018
Electrothermal deterioration factors in gold planar inductors designed for microscale bio-applications
Rizou M, Prodromakis T
In this study, we present the fabrication of wafer level micro-inductors, designed for contactless neuro-stimulation in vitro, along with an electrothermal study testing the influence of thermal phenomena to their performance. The electrical performance of all micro-scale electromagnetic components is hampered by two dominant factors: Joule heating and electromigration. The scope of the study is to evaluate how these phenomena change the electrical behaviour of the samples during activation. We experimentally define the safe area of operation across six types of samples with different geometric characteristics and we extract useful information for the reliability of the samples by comparing their median failure times. Our findings present the activation restrictions which should be taken into account in order to avoid the thermal degradation of the components, while at the same time could be used as design guidelines for similar geometries.
October 2018
Conduction mechanisms at distinct resistive levels of Pt/TiO2-x/Pt memristors
L. Michalas, S. Stathopoulos, A. Khiat, and T. Prodromakis
Resistive random access memories (RRAMs) are considered as key enabling components for a variety of emerging applications due to their capacity to support multiple resistive states. Deciphering the underlying mechanisms that support resistive switching remains to date a topic of debate, particularly for metal-oxide technologies, and is very much needed for optimizing their performance. This work aims to identify the dominant conduction mechanisms during switching operation of Pt/TiO2-x/Pt stacks, which is without a doubt one of the most celebrated ones. A number of identical devices were accordingly electroformed for acquiring distinct resistive levels through a pulsing-based and compliance-free protocol. For each obtained level, the switching current-voltage (I-V) characteristics were recorded and analyzed in the temperature range of 300 K–350 K. This allowed the extraction of the corresponding signature plots revealing the dominant transport mechanism for each of the I-V branches. Gradual (analogue) switching was obtained for all cases, and two major regimes were identified. For the higher resistance regime, the transport at both the high and low resistive states was found to be interface controlled due to Schottky emission. As the resistance of devices reduces to lower levels, the dominant conduction changes from an interface to the core-material controlled mechanism. This study overall supports that engineering the metal-oxide/metal electrode interface can lead to tailored barrier modifications for controlling the switching characteristics of TiO2 RRAM.
September 2018
A technology agnostic RRAM characterisation methodology protocol
Spyros Stathopoulos, Loukas Michalas, Ali Khiat, Alexantrou Serb and Themis Prodromakis
The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and affordable and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of standard characterisation protocols for fair benchmarking. At the same time, opportunities for innovation are missed by focusing on excessively narrow performance aspects. To that end our work presents a complete, technology agnostic, characterisation methodology based on established techniques that are adapted to memristors/RRAM characterisation needs. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to benchmarking across a variety of electrical performance metrics that can in turn support the generation of device models
September 2018
Electrical characteristics of interfacial barriers at metal—TiO2 contacts
Loukas Michalas, Ali Khiat, Spyros Stathopoulos and Themis Prodromakis
The electrical properties of thin TiO2 films have recently been extensively exploited with the aim of enabling a variety of metal-oxide electron devices: unipolar and bipolar semiconductor devices and/or memristors. In these efforts, investigations into the role of TiO2 as active material were the main focus; however, electrode materials are equally important. In this work we address this point by presenting a systematic quantitative electrical characterization study on the interface characteristics of metal-TiO2-metal structures. Our study employs typical contact materials that are used both as top and bottom electrodes in a metal-TiO2-metal setting. This allows an investigation of the characteristics of the interfaces as well as holistically studying an electrode's influence on the opposite interface, referred to in this work as the top/bottom electrodes inter-relationship. Our methodology comprises the recording of current–voltage (I–V) characteristics from a variety of solid-state prototypes in the temperature range of 300 K –350 K, and their analysis through appropriate modelling. Clear field- and temperature-dependent signature plots were also obtained, so as to shine more light on the role of each material as top/bottom electrodes in metal-TiO2-metal configurations. Our results highlight that these are not conventional metal–semiconductor contacts, and that several parameters are involved in the formation of the interfacial barriers, such as the electrode's position (atop or below the film), the electronegativity, the interface states, and even the opposite interface electrode material. Overall, our study provides a useful database for selecting appropriate electrode materials in TiO2-based devices, offering new insights into the role of electrodes in metal-oxide electronics applications.
July 2018
Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons
E Covi, R George, J Frascaroli, S Brivio, C Mayr, H Mostafa, G Indiveri and S Spiga
Biologically plausible neuromorphic computing systems are attracting considerable attention due to their low latency, massively parallel information processing abilities, and their high energy efficiency. To achieve these features neuromorphic silicon neuron circuits need to be integrated with plastic synapse circuits capable of on-line learning and storage of synaptic weights. Within this context, memristive devices play a key role thanks to their non-volatility, scalability, and compatibility with the complementary metal–oxide–semiconductor fabrication process. However, neuro-memristive systems are still facing difficult challenges for implementing efficient learning protocols. Here, we propose and demonstrate in hardware a spike-driven threshold-based learning rule which goes beyond conventional spike-timing dependent plasticity mechanisms, by also taking into account the neuron membrane potential and its firing rate. The mixed memristive–neuromorphic system we demonstrate comprises an oxide-based memristive synapse device placed between two silicon neurons implemented on a neuromorphic chip that comprises the proper interfacing and spike-based learning circuits designed to drive the memristive elements. We show how the system is able to emulate in real-time weight dependent post-synaptic activity and drive synaptic weight updates at the memristive synapse level following the spike-driven learning rule presented. We validate this spike-based learning mechanism with experimental results and quantify the system performance with basic learning experiments.
June 2018
Seamlessly fused digital-analogue reconfigurable computing using memristors
Alexantrou Serb, Ali Khiat & Themistoklis Prodromakis
As the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Emerging nanoelectronics technologies bring forth new prospects yet a significant rethink of electronics design is required for realising their full potential. Here we lay the foundations of a design approach that fuses analogue and digital thinking by combining digital electronics with analogue memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and capable of performing analogue computation at a power cost close to digital. The versatility and benefits of our approach are experimentally showcased through a hardware data clusterer and an analogue NAND gate.
May 2018
An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation
Abbey T, Serb A, Vasilakis N, Michalas L, Khiat A, Stathopoulos S, Prodromaki
Environmental conditions can greatly affect the performance of semiconductor devices. Great sophistication has thus gone into developing versatile systems that allow benchmarking of operating characteristics under a variety of temperature and humidity conditions. Recently, Resistive Random Access Memory (RRAM) technologies, also known as memristors, have received a lot of attention for memory and computing applications. This interest is showcased by several reports on technology and applications developments, as well as developments on the underpinning infrastructure, i.e. models and characterization tools, that renders such technologies useful. Several international research groups and companies are nowadays using ArC One™, a versatile instrument that allows en masse characterization of RRAM technologies, as has been presented previously in several demo sessions at ISCAS. In this work, we present a newly developed module that expands ArC One™ capabilities through incorporating an environmental control system. The proposed module condenses the functionality of significantly larger, more complex and higher cost systems into a low cost, small form-factor and user friendly desktop-operated device. The system allows for temperature, atmospheric composition and humidity control and can be used for studying the impact of such settings on the electrical characteristics of RRAM technologies.
May 2018
Benchmarking Analogue Performance of Emerging Random Access Memory Technologies
Stathopoulos S, Khiat A, Serb A, Prodromakis T
In this work we present an evaluation routine aimed towards assessing the multibit capability of Resistive Random Access Memory (RRAM) technologies. We illustrate a characterization methodology for the maximum possible exploitation of the resistive states of a RRAM cell. Our characterization routine consists of a three phase algorithm: during the first it infers the polarity needed to induce a change in the device's conductance; the second stabilizes the resistive states of the device into a baseline resistance and during the third a sequence of pulses of increasing amplitude is used to determine the actual resistive states. This technology-agnostic methodology allows for efficient and high resolution partitioning of the cell's resistive operating range allowing them to operate in a truly analogue fashion. Demonstrating the maximum potential of RRAM cells in terms of closely packed resistive states can open new avenues for research in non-volatile memories, reconfigurable electronics and neuromorphic applications.
May 2018
High-sensitivity memristor-based threshold detection
Serb A, Prodromakis T
The ability to read brain activity across large swathes of cortex at very high resolution both spatially and temporally is a holy grail objective of modern neuroscience. In this endeavour, the minuteness of neural signals arriving from needle probes (10s to 100s of μV) poses a significant challenge, typically solved using high spec amplifiers. However, when the objective is to detect neural spikes the input signals of interest are inherently sparse, and much energy is spent amplifying data points that will be ultimately discarded. In this work we propose that a possible solution is to distance ourselves from the need to amplify the neural waveforms, and instead opt for performing threshold detection directly on the input signal; which is often sufficient to detect neural spiking. We thus present a high sensitivity threshold detection circuit concept that uses its offset voltage as the reference threshold and thus directly transforms differential input signal samples into digital values. The use of memristive devices within the design allows us to finely tune the detector's offset voltage, thus ensuring sufficient operational flexibility. Using SPICE simulations we demonstrate an exemplar design built using our concept. First we shown its functionality and then we proceed to examine how: i) mismatch at strategically chosen devices affects the amplifier's offset voltage and ii) changing the resistive state of the memristive devices involved helps the designer control the offset voltage.
May 2018
Processing big-data with Memristive Technologies: Splitting the Hyperplane Efficiently
A. Serb; G. Papandroulidakis; A. Khiat; T. Prodromakis
An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include threshold logic and receptive field based classifiers that are presented within the context of a unified perspective.
May 2018
Live Demonstration: An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation
T. Abbey; A. Serb; N. Vasilakis; L. Michalas; A. Khiat; S. Stathopoulos; T. Prodromakis
We demonstrate an environmental control system for testing Resistive Random Access Memory technologies under accurately controlled humidity and temperature. The demonstrated system compresses the functionality of existing environmental control systems into a low cost, desktop-size solution, aimed at providing results quickly and with minimum installation and running overheads.
May 2018
Live Demonstration: Benchmarking Analogue Performance of Emerging Random Access Memory Technologies
Spyros Stathopoulos; Ali Khiat; Alexantrou Serb; Themis Prodromakis
In this demo we present a comprehensive solution for benchmarking the multibit capabilities of resistive memory cells using sequential programming pulses. The algorithm is presented through a rich graphical user interface that allows the user to fully tune the benchmarking parameters..
May 2018
Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates
G. Papandroulidakis; A. Khiat; A. Serb; S. Stathopoulos; L. Michalas; T. Prodromakis
With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.
March 2018
Sub 100 nW Volatile Nano-Metal-Oxide Memristor as Synaptic-Like Encoder of Neuronal Spikes
Isha Gupta, Alexantrou Serb, Ali Khiat, Ralf Zeitler, Stefano Vassanelli, Themistoklis Prodromakis
Advanced neural interfaces mediate a bioelectronic link between the nervous system and microelectronic devices, bearing great potential as innovative therapy for various diseases. Spikes from a large number of neurons are recorded leading to creation of big data that require online processing under most stringent conditions, such as minimal power dissipation and on-chip space occupancy. Here, we present a new concept where the inherent volatile properties of a nano-scale memristive device are used to detect and compress information on neural spikes as recorded by a multielectrode array. Simultaneously, and similarly to a biological synapse, information on spike amplitude and frequency is transduced in metastable resistive state transitions of the device, which is inherently capable of self-resetting and of continuous encoding of spiking activity. Furthermore, operating the memristor in a very high resistive state range reduces its average in-operando power dissipation to less than 100 nW, demonstrating the potential to build highly scalable, yet energy-efficient on-node processors for advanced neural interfaces.
December 2017
Interface Asymmetry Induced by Symmetric Electrodes on Metal–Al:TiO x–Metal Structures
Michalas L, Trapatseli M, Stathopoulos S, Cortese S, Khiat A, Prodromakis T
Emerging memory technologies have sparked great interest in studying a variety of materials that can be employed in metal-insulator-metal topologies to support resistive switching. While the majority of reports focus on identifying appropriate materials that can be used as active core layers, the selection of electrodes also impacts the performance of such memory devices. Here, both the top and the bottom interfaces of symmetric Metal-Al:TiO x -Metal structures have been investigated by the analysis of their current versus voltage characteristics in the temperature range of 300-350 K. Three different metals were utilized as electrodes, Nb, Au, and Pt, for covering a wide range of work function and electronegativity values. Despite their symmetric structure, the devices were found to exhibit asymmetric performance with respect to the applied bias polarity. Clear signature plots indicating thermionic emission over the interface Schottky barriers have been obtained. The asymmetry between the top and the bottom interfaces was further evaluated by the values of the potential barrier heights and by the barrier lowering factors, both calculated from the experimental data. This study highlights the importance of the interface effects and proves that in addition to film doping, proper (top/bottom) metal selection, and interface engineering should also be exploited for developing thin film metal oxide based devices with tailored electrical characteristics.
October 2016
Enabling technologies for very large-scale synaptic electronics (book)
Editors: Themis Prodromakis, Alexantrou Serb
In this research topic, we wish to provide an overview of what constitutes state-of-the-art in terms of enabling technologies for very large scale synaptic electronics, with particular stress on innovative nanoelectronic devices and circuit/system design techniques that can facilitate the development of very large scale brain-inspired electronic systems. Specifically we welcome contributions including (but not limited to) advances in the following:

1) Emerging technologies and devices for reproducing the physics and the dynamics of real synapses (i.e. synaptic emulators), ideally on timescale ranges matching the broadness of biological timescales.
2) Emerging technologies and devices for reproducing good approximations of synaptic behavior (i.e. synaptic simulators), ideally on timescales found in biology.
3) Memory structures exhibiting differing degrees of volatility (including a) fully non-volatile over long time ranges -months-, b) fully volatile and c) devices exhibiting more than one degree of volatility at the same time -e.g. featuring a volatile and a non-volatile component-).
4) Electronic architectures that support or ideally actively exploit the characteristics of inherently unreliable devices.
5) Examples of applications or entire domains of applications where such synaptic electronics could prove of great utility.
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