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Our vision is to rejuvenate modern electronics by developing and enabling a new approach to electronic systems where reconfigurability, scalability, operational flexibility/resilience, power efficiency and cost-effectiveness are combined. 

Below is a list of our current publications helping us work toward our vision. 

 

Text Classification in Memristor-based Spiking Neural Networks
Jinqi Huang, Alex Serb, Spyros Stathopoulos, Themis Prodromakis
Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based spiking neural networks in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained spiking neural networks with memristor models: 1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or 2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches. This investigation further indicates that the simulation using statistic memristor models in the two approaches presented by this paper can assist the exploration of memristor-based SNNs in natural language processing tasks.
A tool for emulating neuromorphic architectures with memristive models and devices
Jinqi Huang, Spyros Stathopoulos, Alex Serb, and Themis Prodromakis
Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware
accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of
neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.
Hardware-efficient compression of neural multi-unit activity using machine learning selected static Huffman encoders
Oscar W Savolainen, Zheng Zhang, Peilong Feng, Timothy G Constandinou
Recent advances in intracortical brain machine interfaces (iBMIs) have demonstrated the feasibility of using our thoughts; by sensing and decoding neural activity, for communication and cursor control tasks. It is essential that any invasive device is completely wireless so as to remove percutaneous connections and the associated infection risks. However, wireless communication consumes significant power and there are strict heating limits in cortical tissue. Most iBMIs use Multi Unit Activity (MUA) processing, however the required bandwidth can be excessive for large channel counts in mm or sub-mm scale implants. As such, some form of data compression for MUA iBMIs is desirable.
An Open-Source RRAM Compiler
Dimitris Antoniadis, Andrea Mifsud, Peilong Feng, Timothy G. Constandinou
Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.
Distributed neural interfaces: challenges and trends in scaling implantable technology
Katarzyna M Szostak, Peilong Feng, Federico Mazza, Timothy G Constandinou
Current implantable neural interfaces, both clinically available solutions and research tools, rely on a limited number of implanted devices (from one to few units). This factor, aside from the obvious spatial resolution limitations, does not conform to the paradigm of the brain as a massively parallel computational system and creates a bottleneck in the amount of information that could be exchanged between the brain and an external processing unit. This issue has fuelled recent research efforts towards the study of distributed neural interfaces, systems that depend on a network of implanted nodes. Such configuration allows to spread of the overall complexity across multiple devices, which can now be more easily scaled down in size and individual power consumption, improving their conformity with the surrounding tissue, which is a major concern in current monolithic solutions. However, this architecture brings a new set of challenges ranging from the optimization of ultra-low-power electronics, through the formulation of a wireless transmission scheme for efficient power delivery and data transfer to the investigation of novel materials and methods for the fabrication of micro-scale, long-term reliable implants. This chapter outlines state of the art and describes design considerations for the future autonomous, wireless distributed neural implants. Aspects of miniaturization and chronic stability of devices including materials choice, implantation procedure, packaging strategies and microelectrode types are described, alongside a discussion on different modalities to achieve wireless power transfer and data telemetry.
Open-source memory compiler for automatic RRAM generation and verification
Dimitrios Antoniadis, Peilong Feng, Andrea Mifsud, Timothy G Constandinou
The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility.
Analogue front-end design for neural recording
Michal Maslik, Lieuwe B Leene, Timothy G Constandinou
There exist a number of key challenges in designing analogue front-end (AFE) recording systems to observe neural activity. These include a limited signal-to-noise ratio (SNR) of the neural biopotential signal itself, microvolt-level amplitudes, relatively low frequency signals and bandwidth, non-ideal electrochemical electrode properties resulting in added noise, DC drift, etc. Furthermore, there is a drive towards high channel count (and high density) systems incorporating hundreds or thousands of channels. The instrumentation in each channel needs to achieve low noise amplification, signal conditioning and digitisation with a minimal power consumption while achieving high noise efficiency and rejecting the sub-Hz electrode offset potential without the use of external passive components. Therefore, such systems should ideally be a fully integrated single-chip solution.
Autonomous wireless system for robust and efficient inductive power transmission to multi-node implants
P Feng, TG Constandinou
A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed ‘swarm’ of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network.
A CMOS-based Characterisation Platform for Emerging RRAM Technologies
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G Constandinou
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device's resistance range to be between 1k and 10M with a minimum voltage range of 1.5V on the device.
Negative effect of cations out-diffusion and auto-doping on switching mechanisms of transparent memristor devices employing ZnO/ITO heterostructure
Firman Mangasa Simanjuntak, Sridhar Chandrasekaran, Debashis Panda, Sailesh Rajasekaran, Cut Rullyani, Govindasamy Madhaiyan, Themistoklis Prodromakis, Tseung-Yuen Tseng
An excessive unintentional out-diffused In atom into the switching layer is a potential threat to the switching stability of memristor devices having indium tin oxide (ITO) as the electrode. We suggest that the physical factor (bombardment of Ar ions and bombardment-induced localized heat during ZnO deposition) and chemical factor (bonding dissociation energy, point defects, and bond length of atoms) are responsible for promoting the out-diffusion. The In atom acts as dopant in the ZnO lattice that degenerates the ZnO insulative behavior. Furthermore, the In ions take part in the conduction mechanism where they may compete with other mobile species to form and rupture the filament, and hence, deteriorate the switching performance. We propose a facile UV/O3 (UVO) treatment to mitigate such damaging effects.
UV induced resistive switching in hybrid polymer metal oxide memristors
Spyros Stathopoulos, Ioulia Tzouvadaki, Themis Prodromakis
There is an increasing interest for alternative ways to program memristive devices to arbitrary resistive levels. Among them, light-controlled programming approach, where optical input is used to improve or to promote the resistive switching, has drawn particular attention. Here, we present a straight-forward method to induce resistive switching to a memristive device, introducing a new version of a metal-oxide memristive architecture coupled with a UV-sensitive hybrid top electrode obtained through direct surface treatment with PEDOT:PSS of an established resistive random access memory platform. UV-illumination ultimately results to resistive switching, without involving any additional stimulation, and a relation between the switching magnitude and the applied wavelength is depicted. Overall, the system and method presented showcase a promising proof-of-concept for granting an exclusively light-triggered resistive switching to memristive devices irrespectively of the structure and materials comprising their main core, and, in perspective can be considered for functional integrations optical-induced sensing.
The FABulous Open eFPGA Ecosystem in Action-From Specifications to Chips to Running Bitsteams
Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch
This demonstration shows the steps a designer has to take to specify and implement a chip with an embedded FPGA (eFPGA) using the FABulous open-source toolchain. We also show how the architecture graph is automatically generated for the open-source FPGA CAD tools (Yosys, ABC, nextpnr) to compile Verilog all the way to a bitstream. Ultimately, we demonstrate such bitstreams running on our FlexBex chip, which integrates an Ibex RISC-V core from lowRISC together with a FABulous eFPGA. The system supports multiple partially reconfigurable regions for hosting reconfigurable instruction set extensions, and the fabric provides logic, DSP, and memory slices.
How to Shrink My FPGAs—Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics
King Lok Chung, Nguyen Dao, Jing Yu, Dirk Koch
Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (= speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity.
The Future of FPGA Acceleration in Datacenters and the Cloud
Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds.
An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing (2022)
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).
Selectively biased tri-terminal vertically-integrated memristor configuration (2022)
Vasileios Manouras, Spyros Stathopoulos, Alex Serb, Themis Prodromakis
Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.
Memristor-Based Pass Gate for FPGA Programmable Routing Switch. ISCAS 2021.
Dirk Kock and Nguyen Dao
The advancement of memristor technologies has recently attracted huge interest in exploiting their superior potential properties for enabling hybrid memristor-CMOS systems. This work presents a memristor-based Pass Gate - mPG, as a primitive cell as well as its deployment for implementing programmable routing switches targeting FPGAs. The mPG, consists of a transistor and output buffer(s) and can be used to discriminate resistance states for both binary and multi-state memristor technologies without additional circuitry. The proposed routing structure eliminates leakage current and avoids degrading memristor’s characteristics due to voltage drops, which are essential factors for building reliable large-scale digital systems like FPGAs. Simulation results of mPG-based switches show that the gate can be deployed for a wide range of memristor resistance with a switching delay in the subnanosecond range
Memristor-based Pass Gate Targeting for FPGA Look-Up Table. 2021, International Conference on Electronics, Information, and Communication (ICEIC)
Nguyen Dao and Dirk Koch
This work proposes a memristor-based Pass Gate - mPG, as a primitive cell for translating memristor resistance states into logic targeting for FPGA Look-Up Tables (LUTs). The mPG consists of a pass transistor with buffers, and it can work with both binary and multibit memristors. The utilization of mPGs for the configuration bit storage in a new LUT architecture based on multibit memristors is introduced. Unlike other prior structures, the proposed architecture not only eliminates leakage current and extra sense amplifier/comparator circuitry but also prevents degrading memristor's characteristics; thus, more reliable systems can be developed. Simulation results show that the gate can be deployed for a wide range of memristor's resistance with a switching delay in the nanosecond range. Physical implementations of multibit memristor-based LUTs demonstrate that up to 80% of the design area and/or the number of transistors could be saved in comparison to standard SRAM-based designs. Furthermore, mPG-based design considerations are thoroughly analyzed and presented.
FABulous: an Embedded FPGA. 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Nguyen Dao and Dirk Koch
At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source FPGA framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as FPGA CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded FPGA fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node.
FlexBex: A Framework for RISC-V and Embedded FPGA Hybrids for Reconfigurable Instruction Extensions. 2020 International Conference on Field-Programmable Technology
Nguyen Dao and Dirk Koch
This paper presents an all open-source framework for adding embedded FPGAs into RISC-V CPUs. In our approach, an eFPGA is directly coupled with the CPU, and through supporting partial reconfiguration, instructions can be swapped at runtime. The eFPGA fabric is tiled into multiple slots in order to host different instructions in parallel, and multiple slots can be combined for hosting more complex instructions. Instructions can be swapped without interrupting the CPU, and instructions can have a different number of execution cycles to provide more flexibility for instruction implementations. Our case study integrates an Ibex RISC-V core from lowRISC together with our custom embedded FPGA supporting multiple regions, with logic, DSP, and Register File slices. This system had been taped out in a 180um TSMC process.
UV Induced Resistive Switching in Hybrid Polymer Metal Oxide Memristors - Scientific Reports - Dec 2020
Stathopoulos, Spyridon and Tzouvadaki, Ioulia
There is an increasing interest for alternative ways to program memristive devices to arbitrary resistive levels. Among them, light-controlled programming approach, where optical input is used to improve or to promote the resistive switching, has drawn particular attention. Here, we present a straight-forward method to induce resistive switching to a memristive device, introducing a new version of a metal-oxide memristive architecture coupled with a UV-sensitive hybrid top electrode obtained through direct surface treatment with PEDOT:PSS of an established resistive random access memory platform. UV-illumination ultimately results to resistive switching, without involving any additional stimulation, and a relation between the switching magnitude and the applied wavelength is depicted. Overall, the system and method presented showcase a promising proof-of-concept for granting an exclusively light-triggered resistive switching to memristive devices irrespectively of the structure and materials comprising their main core, and, in perspective can be considered for functional integrations optical-induced sensing.
Bidirectional Volatile Signatures of Metal-Oxide Memristors--Part I: Characterization, IEEE Transactions on Electron Devices Sept 2020
Christos Giotis, Alex Serb, Spyros Stathopoulos, Loukas Michalas, Ali Khiat and Themis Prodromakis
The multistate capabilities as well as the intrinsic integrating properties of memristors deem them suitable candidates for the realization of novel neuromorphic applications. To date, much of their prestige arises mostly from the versatility that is promised by the nonvolatile device families. However, memristors also exhibit volatile characteristics, which for as long as they remain unknown, will hinder their integration to large-scale applications. In this article, we present a comprehensive study for characterizing the relaxation dynamics of TiOₓ resistive RAM (RRAM) devices within a predefined volatility framework. These dynamics are tightly linked to the total energy of stimulation, and device relaxation can be accurately described using simple mathematical models. Moreover, we show that RRAM volatility is bidirectional and that relaxation time constants heavily depend on the level of invasiveness caused by programming stimulation. Our work further includes a demonstration of how volatility can be characterized within a specific time window. Moreover, our protocol can be altered to fit the specific needs of potential applications. We anticipate that the universality of our method can act as a stepping stone toward the understanding and modeling of volatile memristors across different technologies and materials, enabling the realization of a new family of time-related applications.
Memristor-Enabled Reconfigurable Integrated Circuits. 2020 International Conference on Electronics, Information, and Communication (ICEIC)
Jakub Szypicyn, Christos Papavassiliou, Georgios Papandroulidakis, Geoff Merrett, Alex Serb, Spyros Stathopoulos, Themis Prodromakis
The holy grail of analogue integrated circuit design is adjustable analogue delay element. Of course, all analogue circuits are filters. Internal delays impose overall low-pass character to all circuits so that broadband amplifiers are lowpass filters, while high-pass amplifiers are in fact band-pass filters.
Suboxide interface induces digital-to-analog switching transformation in all Ti-based memristor devices. Appl. Phys. Lett 2020
Chang L-Y, Simanjuntak FM, Hsu C-L, Chandrasekaran S, Tseng T-Y
Oxidation of TiN is a diffusion-limited process due to the high stability of the TiN metallic state at the TiN/TiO2 junction. Hence, the TiN/TiO2/TiN device being the inability to form a suitable interfacial layer results in the exhibition of abrupt current (conductance) rise and fall during the set (potentiation) and reset (depression) processes, respectively. Interfacial engineering by depositing Ti film served as the oxygen gettering material on top of the TiO2 layer induces a spontaneous reaction to form a TiOx interfacial layer (due to the low Gibbs free energy of suboxide formation). Such an interface layer acts as an oxygen reservoir that promotes gradual oxidation and reduction during the set and reset processes. Consequently, an excellent analog behavior having a 2-bit per cell and robust epoch training can be achieved. However, a thick interfacial layer may degrade the switching behavior of the device due to the high internal resistance. This work suggests that interfacial engineering could be considered in designing high-performance analog memristor devices.
A Fast, Highly Flexible and Transparent TaOx-based Environmentally Robust Memristor for Wearable and Aerospace Application. ACS Appl. Electron. Mater 2020
Rajasekaran S, Simanjuntak FM, Panda D, Chandrasekarang S, Aluguri R, Saleem A, Tseng T-Y.
Memristor devices that can operate at high speed with high density and non-volatile capabilities have great potential for the development of high data storage and robust wearable devices. However, in real-time the performance of memristors are challenged by their instability towards harsh working conditions such as high temperature, extreme humidity, photo irradiation and mechanical bending. Herein, we introduce a TaOx/AlN based flexible and transparent memristor device having stable endurance under extreme 2 mm bending (for more than 107 cycles) with ON/OFF ratio of more than 2 orders of magnitude at 25 ns rapid switching. This device performs excellent flexibility under extreme bending conditions (bending radius of 2 mm) even with intense ultraviolet radiation. A thin AlN insertion layer having low dielectric and high thermal conductivity play a crucial role in improving the switching stability and device flexibility. In particular, the devices exhibit excellent minimum switching fluctuations under UV irradiations, 105 s nonvolatility retention at high temperature (135˚C), various gas ambient and, damp heat test (humidity 95.5%, 83˚C) due to the indium metal drift during switching process and high bonding energy of Ta-O. Most importantly, direct observation of indium metal strongly anchored in TaOx switching layer during switching process is reported for the first time via transmission electron microscopy which provides clear insights on the switching phenomenon. Furthermore, results of electrical and material analyses explain that our facile device design has excellent potential for wearable and aerospace applications.
Monitoring PSA levels as chemical state-variables in metal-oxide memristors - Scientific Reports 2020
Ioulia Tzouvadaki, Spyros Stathopoulos, Tom Abbey, Loukas Michalas, Themis Prodromakis
Medical interventions increasingly rely on biosensors that can provide reliable quantitative information. A longstanding bottleneck in realizing this, is various non-idealities that generate offsets and variable responses across sensors. Current mitigation strategies involve the calibration of sensors, performed in software or via auxiliary compensation circuitry thus constraining real-time operation and integration efforts. Here, we show that bio-functionalized metal-oxide memristors can be utilized for directly transducing biomarker concentration levels to discrete memory states. The introduced chemical state-variable is found to be dependent on
the devices’ initial resistance, with its response to chemical stimuli being more pronounced for higher resistive states. We leverage this attribute along with memristors’ inherent state programmability for calibrating a biosensing array to render a homogeneous response across all cells. Finally, we demonstrate the application of this technology in detecting Prostate
Specific Antigen in clinically relevant levels (ng/ml), paving the way towards applications in large multi-panel assays.
Memristor-based Reconfigurable Circuits: Challenges in Implementation, 2020 International Conference on Electronics, Information, and Communication (ICEIC)
Nguyen Cong Dao and Dirk Koch
The emergence of memristor technologies has recently received much attention due to their promising features, expecting to be a key driver in the post-CMOS era. With its ultra-low power, higher density capability and non-volatile characteristics, memristor technology is considered as the best candidate to replace SRAM cells or be employed for routing in digital reconfigurable systems. Although memristor-based reconfigurable circuits can offer many advantages over the conventional CMOS designs, limitations in the utilization of memristor technologies such as electroforming or programming structures have not been thoroughly considered and discussed. This work looks into recent trends in exploiting memristor technologies in reconfigurable circuits and then discusses implementation challenges like memristor programming, reliability and operation of memristor-based memory cells for digitally reconfigurable circuits.
A mixed-signal spatio-temporal signal classifier for on-sensor spike sorting - IEEE International Symposium on Circuits and Systems, ISCAS 2020, Seville, October 2020
G.Haessig, D.Garcia-Lesta, G.Lenz, R.Benosman, P.Dudek
Neuromorphic systems provide an alternative to conventional computing hardware, promising low-power operation suitable for sensory-processing and edge computing. In this paper, we present a mixed-signal processing system designed to provide on-sensor classification of signals obtained from multielectrode array neural recordings. The designed circuits implement a real-time spike sorting algorithm, and operate on signals represented by asynchronous event streams. We combine analog circuits computation primitives (temporal surface generation, distance computation, winner-take-all) to implement a spatiotemporal clustering algorithm, classifying signals acquired by
neighbouring electrodes. The prototype chip has been submitted for fabrication in a 180nm CMOS technology. The circuits are designed to fit, alongside signal conditioning and conversion circuits, in the area under the recording electrodes (below 80x80um per electrode). Circuit implementation details and simulation results are presented. The expected neural spike recognition rates of 75% in a single-layer network and 88% in a 2-layer network are comparable with a software implementation, while the system is designed to provide a low-power embedded real-time solution.
This work provides a foundation towards the design of a large scale neuromorphic processing system, to be embedded in brainmachine interfaces.
A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing - Philosophical Transactions A - December 2019
A. Serb, I. Kobyzev, J. Wang and T. Prodromakis
One of the main, long-term objectives of artificial intelligence is the creation of thinking machines. To that end, substantial effort has been placed into designing cognitive systems; i.e. systems that can manipulate semantic-level information. A substantial part of that effort is oriented towards designing the mathematical machinery underlying cognition in a way that is very efficiently implementable in hardware. In this work, we propose a ‘semi-holographic’ representation system that can be implemented in hardware using only multiplexing and addition operations, thus avoiding the need for expensive multiplication. The resulting architecture can be readily constructed by recycling standard microprocessor elements and is capable of performing two key mathematical operations frequently used in cognition, superposition and binding, within a budget of below 6 pJ for 64-bit operands. Our proposed ‘cognitive processing unit’ is intended as just one (albeit crucial) part of much larger cognitive systems where artificial neural networks of all kinds and associative memories work in concord to give rise to intelligence.
An Electrical Characterisation Methodology for Bench-marking Memristive Device Technologies - Scientific Reports volume 9, Article number: 19412 (2019)
Spyros Stathopoulos, Loukas Michalas, Ali Khiat, Alexantrou Serb & Themis Prodromakis
The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies.
A Memristive Switching Uncertainty Model - IEEE Transactions on Electron Devices (Volume: 66, Issue: 7, July 2019)
Spyros Stathopoulos ; Alexantrou Serb ; Ali Khiat ; Maciej Ogorzałek ; Themis Prodromakis
In this paper, we endeavor to evaluate and model switching noise in resistive random access memory (RRAM) devices. Although noise is always present in physical systems, the sources of which can be attributed to many different effects, in this paper, we are focusing our attention on a specific type-switching noise. Using alternating pulse programming and read trains across different voltages, we acquire a large data set below and above the switching threshold and construct what we define as increment plots, ΔR versus R. Then, through a detailed statistical analysis, we quantify the localized uncertainty among consecutive points using a sliding window of up to N points accounting for any statistical artifacts that arise. By separating the data accumulated from programming and read-out and analyzing them individually, we can subtract a baseline noise floor from the overall switching uncertainty. In this way, we effectively decouple it from other noise sources that affect the device at rest. In the end, an F(R, V) surface can be extracted that closely follows the behavior of uncertainty of the device during programming. This modeled surface can be used as an approximation of the noise behavior of the device or it can be readily incorporated as an additional component to existing switching models.
A 3rd Order Time Domain Delta Sigma Modulator with Extended-Phase Detection - 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Lieuwe B Leene and Timothy G. Constandinou
This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feedforward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm 2 and consumes 13.7 μW of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.
An electrical characterisation methodology for identifying the switching mechanism in TiO2 memristive stacks - Scientific Reports volume 9, Article number: 8168 (2019)
L. Michalas, S. Stathopoulos, A. Khiat & T. Prodromakis
Resistive random access memories (RRAMs) can be programmed to discrete resistive levels on demand via voltage pulses with appropriate amplitude and widths. This tuneability enables the design of various emerging concepts, to name a few: neuromorphic applications and reconfigurable circuits. Despite the wide interest in RRAM technologies there is still room for improvement and the key lies with understanding better the underpinning mechanism responsible for resistive switching. This work presents a methodology that aids such efforts, by revealing the nature of the resistive switching through assessing the transport properties in the non-switching operation regimes, before and after switching occurs. Variation in the transport properties obtained by analysing the current-voltage characteristics at distinct temperatures provides experimental evidence for understanding the nature of the responsible mechanism. This study is performed on prototyped device stacks that possess common Au bottom electrodes, identical TiO2 active layers while employing three different top electrodes, Au, Ni and Pt. Our results support in all cases an interface controlled transport due to Schottky emission and suggest that the acquired gradual switching originates by the bias induced modification of the interfacial barrier. Throughout this study, the top electrode material was found to play a role in determining the electroforming requirements and thus indirectly the devices’ memristive characteristics whilst both the top and bottom metal/oxide interfaces are found to be modified as result of this process.
A 68μW 31kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR - 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Lieuwe B. Leene ; Shiva Letchumanan ; Timothy G. Constandinou
This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM S of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm 2 area requirement.
An Analogue-Domain, Switch-Capacitor-Based Arithmetic-Logic Unit - 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Alexander Serb and Themis Prodromakis
The continuous maturation of novel nanoelectronic devices exhibiting finely tuneable resistive switching is rekindling interest in analogue-domain computation. Regardless of domain, a useful computational module is the arithmetic-logic unit (ALU), which is capable of performing one or more fundamental mathematical operations (typical example: addition and subtraction). In this work we report on a design for an analogue ALU (aALU) capable of performing barrel addition and subtraction (i.e. ADD/SUB in modular arithmetic). The circuit only requires 5 minimum-size transistors and 1 capacitor. We show that our aALU is in principle capable of handling 5 bits of information using a single input/output wire. Core power dissipation per operation is estimated to peak at ≈ 59 f J (input operand-dependent) in TSMC's 65 nm technology.
Spike sorting using non-volatile metal-oxide memristors - Faraday discussions 213 511-520
Isha Gupta, Alexantrou Serb, Ali Khiat, Maria Trapatselia and Themistoklis Prodromakisa
efficient computation paradigms for handling neural data in situ; in particular the computationally heavy task of events classification. Here, we demonstrate how the intrinsic analogue programmability of memristive devices can be exploited to perform spike-sorting on single devices. Leveraging the physical properties of nanoscale memristors allows us to demonstrate that these devices can capture enough information in neural signal for performing spike detection (shown previously) and spike sorting at no additional power cost.
Challenges hindering memristive neuromorphic hardware from going mainstream. - Nature Communications volume 9, Article number: 5267 (2018)
Gina C. Adam, Ali Khiat & Themis Prodromakis
Memristive devices have elicited intense research in the past decade thanks to their inherent low voltage operation, multi-bit storage and cost-effective manufacturability. Nonetheless, several outstanding performance and manufacturability challenges have prevented the widespread industry adoption of redox-based memristive matrices. Here, we discuss these challenges in terms of key metrics and propose a roadmap towards realizing competitive memristive-based neuromorphic processing systems.
Conduction mechanisms at distinct resistive levels of Pt/TiO2-x/Pt memristors - Appl. Phys. Lett. 113, 143503 (2018
L. Michalas, S. Stathopoulos, A. Khiat, and T. Prodromakis
Resistive random access memories (RRAMs) are considered as key enabling components for a variety of emerging applications due to their capacity to support multiple resistive states. Deciphering the underlying mechanisms that support resistive switching remains to date a topic of debate, particularly for metal-oxide technologies, and is very much needed for optimizing their performance. This work aims to identify the dominant conduction mechanisms during switching operation of Pt/TiO2-x/Pt stacks, which is without a doubt one of the most celebrated ones. A number of identical devices were accordingly electroformed for acquiring distinct resistive levels through a pulsing-based and compliance-free protocol. For each obtained level, the switching current-voltage (I-V) characteristics were recorded and analyzed in the temperature range of 300 K–350 K. This allowed the extraction of the corresponding signature plots revealing the dominant transport mechanism for each of the I-V branches. Gradual (analogue) switching was obtained for all cases, and two major regimes were identified. For the higher resistance regime, the transport at both the high and low resistive states was found to be interface controlled due to Schottky emission. As the resistance of devices reduces to lower levels, the dominant conduction changes from an interface to the core-material controlled mechanism. This study overall supports that engineering the metal-oxide/metal electrode interface can lead to tailored barrier modifications for controlling the switching characteristics of TiO2 RRAM.
Electrical characteristics of interfacial barriers at metal—TiO2 contacts - Journal of Physics D: Applied Physics, Volume 51, Number 42
Loukas Michalas, Ali Khiat, Spyros Stathopoulos and Themis Prodromakis
The electrical properties of thin TiO2 films have recently been extensively exploited with the aim of enabling a variety of metal-oxide electron devices: unipolar and bipolar semiconductor devices and/or memristors. In these efforts, investigations into the role of TiO2 as active material were the main focus; however, electrode materials are equally important. In this work we address this point by presenting a systematic quantitative electrical characterization study on the interface characteristics of metal-TiO2-metal structures. Our study employs typical contact materials that are used both as top and bottom electrodes in a metal-TiO2-metal setting. This allows an investigation of the characteristics of the interfaces as well as holistically studying an electrode's influence on the opposite interface, referred to in this work as the top/bottom electrodes inter-relationship. Our methodology comprises the recording of current–voltage (I–V) characteristics from a variety of solid-state prototypes in the temperature range of 300 K –350 K, and their analysis through appropriate modelling. Clear field- and temperature-dependent signature plots were also obtained, so as to shine more light on the role of each material as top/bottom electrodes in metal-TiO2-metal configurations. Our results highlight that these are not conventional metal–semiconductor contacts, and that several parameters are involved in the formation of the interfacial barriers, such as the electrode's position (atop or below the film), the electronegativity, the interface states, and even the opposite interface electrode material. Overall, our study provides a useful database for selecting appropriate electrode materials in TiO2-based devices, offering new insights into the role of electrodes in metal-oxide electronics applications.ogical and workable to encircle one’s own banker militarily?
A technology agnostic RRAM characterisation methodology protocol - Applied Physics 2018
Spyros Stathopoulos, Loukas Michalas, Ali Khiat, Alexantrou Serb and Themis Prodromakis
The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and affordable and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of standard characterisation protocols for fair benchmarking. At the same time, opportunities for innovation are missed by focusing on excessively narrow performance aspects. To that end our work presents a complete, technology agnostic, characterisation methodology based on established techniques that are adapted to memristors/RRAM characterisation needs. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to benchmarking across a variety of electrical performance metrics that can in turn support the generation of device models
Seamlessly fused digital-analogue reconfigurable computing using memristors - Nature Communications volume 9, Article number: 2170 (2018)
Alexantrou Serb, Ali Khiat & Themistoklis Prodromakis
As the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Emerging nanoelectronics technologies bring forth new prospects yet a significant rethink of electronics design is required for realising their full potential. Here we lay the foundations of a design approach that fuses analogue and digital thinking by combining digital electronics with analogue memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and capable of performing analogue computation at a power cost close to digital. The versatility and benefits of our approach are experimentally showcased through a hardware data clusterer and an analogue NAND gate.
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