One of the main, long-term objectives of artificial intelligence is the creation of thinking machines. To that end, substantial effort has been placed into designing cognitive systems; i.e. systems that can manipulate semantic-level information. A substantial part of that effort is oriented towards designing the mathematical machinery underlying cognition in a way that is very efficiently implementable in hardware. In this work, we propose a ‘semi-holographic’ representation system that can be implemented in hardware using only multiplexing and addition operations, thus avoiding the need for expensive multiplication. The resulting architecture can be readily constructed by recycling standard microprocessor elements and is capable of performing two key mathematical operations frequently used in cognition, superposition and binding, within a budget of below 6 pJ for 64-bit operands. Our proposed ‘cognitive processing unit’ is intended as just one (albeit crucial) part of much larger cognitive systems where artificial neural networks of all kinds and associative memories work in concord to give rise to intelligence.

The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies.

We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method.

In this paper, we endeavor to evaluate and model switching noise in resistive random access memory (RRAM) devices. Although noise is always present in physical systems, the sources of which can be attributed to many different effects, in this paper, we are focusing our attention on a specific type-switching noise. Using alternating pulse programming and read trains across different voltages, we acquire a large data set below and above the switching threshold and construct what we define as increment plots, ΔR versus R. Then, through a detailed statistical analysis, we quantify the localized uncertainty among consecutive points using a sliding window of up to N points accounting for any statistical artifacts that arise. By separating the data accumulated from programming and read-out and analyzing them individually, we can subtract a baseline noise floor from the overall switching uncertainty. In this way, we effectively decouple it from other noise sources that affect the device at rest. In the end, an F(R, V) surface can be extracted that closely follows the behavior of uncertainty of the device during programming. This modeled surface can be used as an approximation of the noise behavior of the device or it can be readily incorporated as an additional component to existing switching models.

Resistive random access memories (RRAMs) can be programmed to discrete resistive levels on demand via voltage pulses with appropriate amplitude and widths. This tuneability enables the design of various emerging concepts, to name a few: neuromorphic applications and reconfigurable circuits. Despite the wide interest in RRAM technologies there is still room for improvement and the key lies with understanding better the underpinning mechanism responsible for resistive switching. This work presents a methodology that aids such efforts, by revealing the nature of the resistive switching through assessing the transport properties in the non-switching operation regimes, before and after switching occurs. Variation in the transport properties obtained by analysing the current-voltage characteristics at distinct temperatures provides experimental evidence for understanding the nature of the responsible mechanism. This study is performed on prototyped device stacks that possess common Au bottom electrodes, identical TiO2 active layers while employing three different top electrodes, Au, Ni and Pt. Our results support in all cases an interface controlled transport due to Schottky emission and suggest that the acquired gradual switching originates by the bias induced modification of the interfacial barrier. Throughout this study, the top electrode material was found to play a role in determining the electroforming requirements and thus indirectly the devices’ memristive characteristics whilst both the top and bottom metal/oxide interfaces are found to be modified as result of this process.

This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feedforward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm 2 and consumes 13.7 μW of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM S of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm 2 area requirement.

The continuous maturation of novel nanoelectronic devices exhibiting finely tuneable resistive switching is rekindling interest in analogue-domain computation. Regardless of domain, a useful computational module is the arithmetic-logic unit (ALU), which is capable of performing one or more fundamental mathematical operations (typical example: addition and subtraction). In this work we report on a design for an analogue ALU (aALU) capable of performing barrel addition and subtraction (i.e. ADD/SUB in modular arithmetic). The circuit only requires 5 minimum-size transistors and 1 capacitor. We show that our aALU is in principle capable of handling 5 bits of information using a single input/output wire. Core power dissipation per operation is estimated to peak at ≈ 59 f J (input operand-dependent) in TSMC's 65 nm technology.

An important cornerstone of data processing is the ability to efficiently capture structure in data and perform data classification. More recently, memristive technologies enabled the incorporation of continuous tuneable resistive elements directly in hardware, thus increasing the efficiency of reconfigurable systems power and area-wise. Memristors are a promising candidate for reconfigurable circuits capable of carrying out classification with physical computing, such as dot-product vector multiplication and accumulation technique. In this work, we demonstrate a novel proof-of-concept memristor-based Digital-In-Analogue-Out logic circuit and present preliminary results highlighting the effect of non-uniform non-linear memristor IV characteristics that result in device-to-device behavioural variation.

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing and benefits which follow from its technological attributes, such as nanoscale dimensions, low-power operation, and multi-state programming. At the same time, the design with CMOS is quickly reaching its physical and functional limitations, and further research toward novel logic families, such as threshold logic gates (TLGs), is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate two-input, three-input, and four-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing a promise as an alternative hardware-friendly implementation of artificial neural networks. Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used toward an in silico classifier.