The operating current regime is found to play a key role in determining the synaptic characteristic of memristor devices. A conduction channel that is formed using high current compliance prior to the synaptic operation results in digital behavior; the high current stimulus forms a complete conductive filament connecting the cathode and anode, and the high electric field promotes abrupt redox reactions during potentiation and depression pulsing schemes. Conversely, the conduction can be reconfigured to produce a filamentary-homogeneous hybrid channel by utilizing the low current stimulus, and this configuration enables the occurrence of analog behavior. The capabilities of memristors showing programmable digital-to-analog or analog-to-digital transformation open a wide range of applications in electronics. We propose a conduction mechanism to explain this phenomenon.

Current implantable neural interfaces, both clinically available solutions and research tools, rely on a limited number of implanted devices (from one to few units). This factor, aside from the obvious spatial resolution limitations, does not conform to the paradigm of the brain as a massively parallel computational system and creates a bottleneck in the amount of information that could be exchanged between the brain and an external processing unit. This issue has fuelled recent research efforts towards the study of distributed neural interfaces, systems that depend on a network of implanted nodes. Such configuration allows to spread of the overall complexity across multiple devices, which can now be more easily scaled down in size and individual power consumption, improving their conformity with the surrounding tissue, which is a major concern in current monolithic solutions. However, this architecture brings a new set of challenges ranging from the optimization of ultra-low-power electronics, through the formulation of a wireless transmission scheme for efficient power delivery and data transfer to the investigation of novel materials and methods for the fabrication of micro-scale, long-term reliable implants. This chapter outlines state of the art and describes design considerations for the future autonomous, wireless distributed neural implants. Aspects of miniaturization and chronic stability of devices including materials choice, implantation procedure, packaging strategies and microelectrode types are described, alongside a discussion on different modalities to achieve wireless power transfer and data telemetry.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

Over the past decade, memristors have been extensively studied for a number of applications, almost exclusively with DC characterization techniques. Studies of memristors in AC circuits are sparse, with only a few examples found in the literature, and characterization methods with an AC input are also sparingly used. However, publications concerning the usage of memristors in this working regime are currently on the rise. Here we propose a "technology agnostic" methodology for memristor testing in certain frequency bands. A measurement process is initially proposed, with specific instructions on sample preparation, followed by an equipment calibration and measurement protocol. This article is structured in a way which aims to facilitate the usage of any available measurement equipment and it can be applied on any type of memristive technology. The second half of this work is centered around the representation of data received from following this process. Bode plot and Nyquist plot representations are considered and the information received from them is evaluated. Finally, examples of expected behaviors are given, characterizing simulated scenarios which represent different internal device models and different switching behaviors, such as capacitive or inductive switching. This study aims at providing a cohesive way for memristor characterization, to be used as a good starting point for frequency applications, and for understanding physical processes inside the devices, by streamlining the measuring process and providing a frame in which data representation and comparison will be facilitated.

This demonstration shows the steps a designer has to take to specify and implement a chip with an embedded FPGA (eFPGA) using the FABulous open-source toolchain. We also show how the architecture graph is automatically generated for the open-source FPGA CAD tools (Yosys, ABC, nextpnr) to compile Verilog all the way to a bitstream. Ultimately, we demonstrate such bitstreams running on our FlexBex chip, which integrates an Ibex RISC-V core from lowRISC together with a FABulous eFPGA. The system supports multiple partially reconfigurable regions for hosting reconfigurable instruction set extensions, and the fabric provides logic, DSP, and memory slices.

The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility.

Memristor is a promising device as a fundamental building block for future unconventional system architectures such as neuromorphic computing, reconfigurable logic, and multibit memories. Therefore, to facilitate circuit design using memristors, accurate and efficient models spanning a wide range of programming voltages and temperatures are required. In the first part of this series, we propose a behavioral model for temperature dependence of nonvolatile switching dynamics of TiO x memristors. We begin by describing pulsed resistance transients (PRTs) of the memristors and then we use a multistage methodology to establish bias and temperature dependence of the model parameters. The proposed model is then shown to accurately describe the PRT characteristics of Pt/TiO x /Au and Pt/TiO x /Pt memristors.

In the second part of this series, we propose a physics-based model for describing the temperature dependence of TiO x -based memristors, both switching and static. We show that the current–voltage ( I – V ) characteristics of memristor in the nonswitching regime, indicating a Schottky emission mechanism, can be described by minor modifications to the Schottky current equation. This leads to a physics-based static I – V compact model. Simultaneously, we show that the temperature dependence of the switching dynamics model parameters naturally emerges as a mere scaling factor from the static I – V model. This is a computationally efficient approach, which does not require any additional parameters to extend the switching dynamics model for incorporating thermal dependence.

There exist a number of key challenges in designing analogue front-end (AFE) recording systems to observe neural activity. These include a limited signal-to-noise ratio (SNR) of the neural biopotential signal itself, microvolt-level amplitudes, relatively low frequency signals and bandwidth, non-ideal electrochemical electrode properties resulting in added noise, DC drift, etc. Furthermore, there is a drive towards high channel count (and high density) systems incorporating hundreds or thousands of channels. The instrumentation in each channel needs to achieve low noise amplification, signal conditioning and digitisation with a minimal power consumption while achieving high noise efficiency and rejecting the sub-Hz electrode offset potential without the use of external passive components. Therefore, such systems should ideally be a fully integrated single-chip solution.

This paper describes preliminary work towards an automated algorithm for labelling Neuropixel data that exploits the fact that adjacent recording sites are spatially oversampled. This is achieved by combining classical single channel spike sorting with spatial spike grouping, resulting in an improvement in both accuracy and robustness. This is additionally complemented by an automated method for channel selection that determines which channels contain high quality data. The algorithm has been applied to a freely accessible dataset, produced by Cortex Lab, UCL. This has been evaluated to have a accuracy of over 77% compared to a manually curated ground truth.

Memristors have been at the forefront of nanoelectronics research for the last few decades, offering a valuable component to reconfigurable computing. Their attributes have been studied extensively along with applications that leverage their state-dependent programmability in a static fashion. However, practical applications of memristor-based alternating current (ac) circuits have been rather sparse, with only a few examples found in the literature where their use is emulated at higher frequencies. In this work, we study the behavior of metal-oxide memristors under a noninvasive ac perturbation in a range of frequencies, from 10 3 to 10 7 Hz. Metal-oxide memristors are found to behave as RC low-pass filters and they present a variable cut-off frequency when their state is switched, thus providing a window of reconfigurability when used as filters. We further study this behavior across distinct material systems, and we show that the usable reconfigurability window of the devices can be tailored to encompass specific frequency ranges by amending the devices' capacitance. This study extends current knowledge on metal-oxide memristors by characterizing their frequency-dependent characteristics, providing useful insights for their use in reconfigurable ac circuits.

This paper presents an all open-source framework for adding embedded FPGAs into RISC-V CPUs. In our approach, an eFPGA is directly coupled with the CPU, and through supporting partial reconfiguration, instructions can be swapped at runtime. The eFPGA fabric is tiled into multiple slots in order to host different instructions in parallel, and multiple slots can be combined for hosting more complex instructions. Instructions can be swapped without interrupting the CPU, and instructions can have a different number of execution cycles to provide more flexibility for instruction implementations. Our case study integrates an Ibex RISC-V core from lowRISC together with our custom embedded FPGA supporting multiple regions, with logic, DSP, and Register File slices. This system had been taped out in a 180um TSMC process.

A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed ‘swarm’ of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network.

An excessive unintentional out-diffused In atom into the switching layer is a potential threat to the switching stability of memristor devices having indium tin oxide (ITO) as the electrode. We suggest that the physical factor (bombardment of Ar ions and bombardment-induced localized heat during ZnO deposition) and chemical factor (bonding dissociation energy, point defects, and bond length of atoms) are responsible for promoting the out-diffusion. The In atom acts as dopant in the ZnO lattice that degenerates the ZnO insulative behavior. Furthermore, the In ions take part in the conduction mechanism where they may compete with other mobile species to form and rupture the filament, and hence, deteriorate the switching performance. We propose a facile UV/O3 (UVO) treatment to mitigate such damaging effects.

The advancement of memristor technologies has recently attracted huge interest in exploiting their superior potential properties for enabling hybrid memristor-CMOS systems. This work presents a memristor-based Pass Gate - mPG, as a primitive cell as well as its deployment for implementing programmable routing switches targeting FPGAs. The mPG, consists of a transistor and output buffer(s) and can be used to discriminate resistance states for both binary and multi-state memristor technologies without additional circuitry. The proposed routing structure eliminates leakage current and avoids degrading memristor’s characteristics due to voltage drops, which are essential factors for building reliable large-scale digital systems like FPGAs. Simulation results of mPG-based switches show that the gate can be deployed for a wide range of memristor resistance with a switching delay in the subnanosecond range

Detecting neuronal activity for rehabilitation/assistive devices is an example of extreme edge computing, featuring stringent requirements for data bandwidth from implantable acquisition system, low-power consumption and ideally also low latency. Recently, we proposed a neural recording system which detects neural spikes directly on the signals collected from electrophysiological probes. The system achieves power efficiency by utilising a combination of integrative sensing and ultra-fine offset compensation. A central component of this design is a memristive load, which is utilised as a trimming device along the differential branches of the core amplifier, ultimately allowing system offset tuning with μν precision. Previous work has assumed that the memristive device features a linear, or nearly-linear current-voltage (IV) characteristic. In this paper, we study the impact of memristor IV non-linearity on the effective gain and offset compensation capability of the system. Results show that the non-linearity experimentally measured from our in-house metal-oxide memristor technology only induces a small gap between nominal resistive state and static RS (as reflected on the IV). This leads to a very small degradation of gain (≈ 2.5%) and offset compensation (≈ 50% increased offset tuning sensitivity), but very crucially proves that introducing IV non-linearity does not materially change either the extreme offset trimming precision or the overall performance. This was the last conceptual bottleneck identified before practical implementation and it has now been overcome.

In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1 MHz indicates a æ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a æ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.

Electronic technologies that can operate in harsh radiation environments are important in space, nuclear and avionic applications. However, radiation-hardened (rad-hard) integrated circuits often require additional processing and more complex configurations than conventional systems. Here we review the development of low-power, rad-hard electronics, examining the underlying phenomena of radiation-induced electronic failure and the design methodologies available with conventional complementary metal–oxide–semiconductor (CMOS) technologies to mitigate the problem. We also explore the potential use and applications of various emerging memory technologies in rad-hard electronics.

Background: The progress in microtechnology has enabled an exponential trend in the number of neurons that can be simultaneously recorded. The data bandwidth requirement is however increasing with channel count. The vast majority of experimental work involving electrophysiology stores the raw data and then processes this offline; to detect the underlying spike events. Emerging applications however require new methods for local, real-time processing.

New methods: We have developed an adaptive, low complexity spike detection algorithm that combines three novel components for: (1) removing the local field potentials; (2) enhancing the signal-to-noise ratio; and (3) computing an adaptive threshold. The proposed algorithm has been optimised for hardware implementation (i.e. minimising computations, translating to a fixed-point implementation), and demonstrated on low-power embedded targets.

Main results: The algorithm has been validated on both synthetic datasets and real recordings yielding a detection sensitivity of up to 90%. The initial hardware implementation using an off-the-shelf embedded platform demonstrated a memory requirement of less than 0.1 kb ROM and 3 kb program flash, consuming an average power of 130 μW.

Comparison with existing methods: The method presented has the advantages over other approaches, that it allows spike events to be robustly detected in real-time from neural activity in a completely autonomous way, without the need for any calibration, and can be implemented with low hardware resources.

Conclusion: The proposed method can detect spikes effectively and adaptively. It alleviates the need for re-calibration, which is critical towards achieving a viable BMI, and more so with future 'high bandwidth' systems' targeting 1000s of channels.

An oxidizable metal diffusion barrier inserted between the active metal electrode and the switching layer decreases the electroforming voltage and enhances the switching stability and synaptic performances in TaOx-based conducting bridge memristor devices. The TiW barrier layer avoids an excessive metal ion diffusion into the switching layer, while the TiWOx interfacial layer is formed between the barrier and the switching layer. It modulates the oxygen vacancy distribution at the top interface and contributes to the formation and rupture of the metal ion-oxygen vacancy hybrid conducting bridge. We observe that the device that relies upon non-hybrid (metal ions only) conducting bridge suffers from poor analogous performance. Meanwhile, the device made with the barrier layer is capable of providing 2-bit memory and robust 50 stable epochs. TaOx also acts as resistance for suppressing and a thermal enhancement layer, which helps to minimize overshooting current. The enhanced analog device with high linear weight update shows multilevel cell characteristics and stable 50 epochs. To validate the neuromorphic characteristic of the devices, a simulated neural network of 100 synapses is used to recognize 10 × 10 pixel images.

At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source FPGA framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as FPGA CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded FPGA fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node.

This work proposes a memristor-based Pass Gate - mPG, as a primitive cell for translating memristor resistance states into logic targeting for FPGA Look-Up Tables (LUTs). The mPG consists of a pass transistor with buffers, and it can work with both binary and multibit memristors. The utilization of mPGs for the configuration bit storage in a new LUT architecture based on multibit memristors is introduced. Unlike other prior structures, the proposed architecture not only eliminates leakage current and extra sense amplifier/comparator circuitry but also prevents degrading memristor's characteristics; thus, more reliable systems can be developed. Simulation results show that the gate can be deployed for a wide range of memristor's resistance with a switching delay in the nanosecond range. Physical implementations of multibit memristor-based LUTs demonstrate that up to 80% of the design area and/or the number of transistors could be saved in comparison to standard SRAM-based designs. Furthermore, mPG-based design considerations are thoroughly analyzed and presented.