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Our vision is to rejuvenate modern electronics by developing and enabling a new approach to electronic systems where reconfigurability, scalability, operational flexibility/resilience, power efficiency and cost-effectiveness are combined. 

Below is a list of our current publications helping us work toward our vision. 

 

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An Open-Source RRAM Compiler
Dimitris Antoniadis, Andrea Mifsud, Peilong Feng, Timothy G. Constandinou
Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.
Distributed neural interfaces: challenges and trends in scaling implantable technology
Katarzyna M Szostak, Peilong Feng, Federico Mazza, Timothy G Constandinou
Current implantable neural interfaces, both clinically available solutions and research tools, rely on a limited number of implanted devices (from one to few units). This factor, aside from the obvious spatial resolution limitations, does not conform to the paradigm of the brain as a massively parallel computational system and creates a bottleneck in the amount of information that could be exchanged between the brain and an external processing unit. This issue has fuelled recent research efforts towards the study of distributed neural interfaces, systems that depend on a network of implanted nodes. Such configuration allows to spread of the overall complexity across multiple devices, which can now be more easily scaled down in size and individual power consumption, improving their conformity with the surrounding tissue, which is a major concern in current monolithic solutions. However, this architecture brings a new set of challenges ranging from the optimization of ultra-low-power electronics, through the formulation of a wireless transmission scheme for efficient power delivery and data transfer to the investigation of novel materials and methods for the fabrication of micro-scale, long-term reliable implants. This chapter outlines state of the art and describes design considerations for the future autonomous, wireless distributed neural implants. Aspects of miniaturization and chronic stability of devices including materials choice, implantation procedure, packaging strategies and microelectrode types are described, alongside a discussion on different modalities to achieve wireless power transfer and data telemetry.
Open-source memory compiler for automatic RRAM generation and verification
Dimitrios Antoniadis, Peilong Feng, Andrea Mifsud, Timothy G Constandinou
The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility.
Analogue front-end design for neural recording
Michal Maslik, Lieuwe B Leene, Timothy G Constandinou
There exist a number of key challenges in designing analogue front-end (AFE) recording systems to observe neural activity. These include a limited signal-to-noise ratio (SNR) of the neural biopotential signal itself, microvolt-level amplitudes, relatively low frequency signals and bandwidth, non-ideal electrochemical electrode properties resulting in added noise, DC drift, etc. Furthermore, there is a drive towards high channel count (and high density) systems incorporating hundreds or thousands of channels. The instrumentation in each channel needs to achieve low noise amplification, signal conditioning and digitisation with a minimal power consumption while achieving high noise efficiency and rejecting the sub-Hz electrode offset potential without the use of external passive components. Therefore, such systems should ideally be a fully integrated single-chip solution.
Autonomous wireless system for robust and efficient inductive power transmission to multi-node implants
P Feng, TG Constandinou
A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed ‘swarm’ of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network.
Negative effect of cations out-diffusion and auto-doping on switching mechanisms of transparent memristor devices employing ZnO/ITO heterostructure
Firman Mangasa Simanjuntak, Sridhar Chandrasekaran, Debashis Panda, Sailesh Rajasekaran, Cut Rullyani, Govindasamy Madhaiyan, Themistoklis Prodromakis, Tseung-Yuen Tseng
An excessive unintentional out-diffused In atom into the switching layer is a potential threat to the switching stability of memristor devices having indium tin oxide (ITO) as the electrode. We suggest that the physical factor (bombardment of Ar ions and bombardment-induced localized heat during ZnO deposition) and chemical factor (bonding dissociation energy, point defects, and bond length of atoms) are responsible for promoting the out-diffusion. The In atom acts as dopant in the ZnO lattice that degenerates the ZnO insulative behavior. Furthermore, the In ions take part in the conduction mechanism where they may compete with other mobile species to form and rupture the filament, and hence, deteriorate the switching performance. We propose a facile UV/O3 (UVO) treatment to mitigate such damaging effects.
The FABulous Open eFPGA Ecosystem in Action-From Specifications to Chips to Running Bitsteams
Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch
This demonstration shows the steps a designer has to take to specify and implement a chip with an embedded FPGA (eFPGA) using the FABulous open-source toolchain. We also show how the architecture graph is automatically generated for the open-source FPGA CAD tools (Yosys, ABC, nextpnr) to compile Verilog all the way to a bitstream. Ultimately, we demonstrate such bitstreams running on our FlexBex chip, which integrates an Ibex RISC-V core from lowRISC together with a FABulous eFPGA. The system supports multiple partially reconfigurable regions for hosting reconfigurable instruction set extensions, and the fabric provides logic, DSP, and memory slices.
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