A carbon-based natural nanocomposite material comprising carbon quantum dots (CQDs) is dispersed in a chitosan matrix. The CQD–chitosan nanocomposite serves as a solid polymer electrolyte layer of a biomemristor with a Au/CQD–chitosan/Al structure. The active layer of the CQD–chitosan nanocomposite is deposited from its solution on top of coplanar asymmetric nanogap (∼15 nm) Al–Au electrodes, patterned via adhesion lithography. The CQD–chitosan biomemristor presents a high on/off ratio (>106) and reproducible and reliable bipolar resistive switching behavior. An endurance of 160 cycles was recorded, while the high and low resistance states remained stable for more than 104 s. This study highlights the potential of both the CQD–chitosan material and nanogap electrode structures for application in nanoscale biocompatible memory devices.

From better resource pooling for FPGA cloud providers to building dynamic execution pipelines at runtime, the capabilities of partial reconfiguration (PR) are waiting to be fully explored. However, the community still fails to materialize PR at scale, and FPGAs are only used as updatable ASICs, hence, omitting the opportunities offered by dynamically reconfiguring FPGAs at runtime. This work proposes a resourceful FPGA bitstream manipulation framework. The proposed tool provides means for parsing, modification, and generation of bitstream files, and it has been open-sourced and demonstrated in a working system. As a distinguished feature, it supports multidie FPGAs (among the 106 Xilinx 7 Series, UltraScale, and UltraScale+ devices), and enables datacenter FPGAs to be used for relocatable PR. Using the versatile tool's built-in (dis)assembler allows for manual bitstream manipulations. Bundled with an efficient bitstream manipulation core, the efficacy is demonstrated by two case studies where we observe 58 - 377x higher bitstream merging throughput than a current state-of-art tool.

This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator using a memristive finite impulse response (FIR) digital-to-analog converter (DAC) in the feedback. To achieve better power and circuit area efficiency, the coefficients of the 8-tap FIR filter are implemented using memristors with programmable resistance in the range of 17.20kΩ to 55.63kΩ . The modulator was designed and simulated using a 180nm standard CMOS technology in addition to a memristor model, which was constructed based on the measured characteristics of the real device behavior. The modulator targets 10kHz signal bandwidth and samples at 10MHz. Simulation results show that the FIR DAC can improve the modulator signal-to-noise and distortion ratio (SNDR) from 44.36dB to 62.29dB with the existence of 5ns RMS jitter at the sampling clock. The FIR DAC still contributes to a better modulator SNDR performance even considering a worst-case 20% resistance variation of the memristors.

Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state (also often referred as multibit, and multi-level) switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multi-state memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multi-state memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.

The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.

Currently, we have no practical emulation solution for analogue and mixed-signal (AMS) circuits, unlike resolutions found for FPGA digital circuit emulation. This paper presents a high Q crystal oscillator circuit emulation based on Wave Digital Filter (WDF). An analogue circuit emulation method was used based on WDFs proposed in [1] to cover the entire flow of transforming an analogue circuit from a SPICE netlist towards FPGA hardware implementation. Although the WDF has been shown to be effective for circuits with linear elements, a proper method for dealing with nonlinear components, such as MOS transistors, is required. [2] proposed a WDF model for MOS transistors that can solve the connectivity problem in traditional nonlinear WDF models while maintaining analogue emulation accuracy and efficiency. As emulation examples, Resistor-Capacitor (RC), Common Source amplifier (CS), and high Q crystal oscillator circuits were implemented in WDF and compared to their SPICE simulations for verification purposes.

Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.

One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.

Recent advances in intracortical brain machine interfaces (iBMIs) have demonstrated the feasibility of using our thoughts; by sensing and decoding neural activity, for communication and cursor control tasks. It is essential that any invasive device is completely wireless so as to remove percutaneous connections and the associated infection risks. However, wireless communication consumes significant power and there are strict heating limits in cortical tissue. Most iBMIs use Multi Unit Activity (MUA) processing, however the required bandwidth can be excessive for large channel counts in mm or sub-mm scale implants. As such, some form of data compression for MUA iBMIs is desirable.

This paper assesses and challenges whether commonly used methods for defining amplitude thresholds for spike detection are optimal. This is achieved through empirical testing of single amplitude thresholds across multiple recordings of varying SNR levels. Our results suggest that the most widely used noise-statistics-driven threshold can suffer from parameter deviation in different noise levels. The spike-noise-driven threshold can be an ideal approach to set the threshold for spike detection, which suffers less from the parameter deviation and is robust to sub-optimal settings.

High-resolution phase shifters have important practical applications in PET scanners, time-to-digital converters, and characterizing of the FPGA resources. This paper presents a fine-grained clock phase-shifting technique based on the FPGAs' clock managers' dynamic phase shifting capability that is commonly available on all recent FPGAs. Our method allows adjusting the phase shift resolution in the sub-picosecond range independent of the operating frequency. Experiments carried out on a Xilinx UltraScale+ FPGA show that phase-shifting resolution can be adjusted down to 88 f s in these devices. To verify the performance of this method, we have deployed it in a delay characterization circuit to measure the FPGA's resources delays. The experiments show that we can measure path delays below 1 ns which is impossible in conventional frequency sweep-based methods and we reach a much finer time resolution.

Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and 2× banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain 170pA current noise floor, 40ns pulse delivery at ±13.5V and 12mA maximum current drive/channel. We then showcase the instrument’s use in performing a selection of three characteristic measurement tasks: (a) current–voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADC). A R-2R digital-to-analog converter (DAC) was implemented with a memristor array and other peripheral circuits. The background calibration detects the error caused by DAC mismatch and corrects it by adjusting the memristor’s memristance 1 in a feedback loop. The implemented circuit takes advantage of the memristor’s small area and multi-state switching property. Simulation results show the feasibility of using memristors to correct mismatch in high-resolution ADC design. The proposed system has been designed in a TSMC 180nm process. Memristors will be laid on the top of the chip via Metal 5 and Metal 6.

Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based spiking neural networks in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained spiking neural networks with memristor models: 1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or 2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches. This investigation further indicates that the simulation using statistic memristor models in the two approaches presented by this paper can assist the exploration of memristor-based SNNs in natural language processing tasks.

In this paper we elaborate and verify a data-driven modelling approach, pertaining to the stochastic trajectory of the memristance upon the application of pulses. Our proposed approach is to model the memristor’s behaviour as a time-homogeneous Markov chain. We introduce a simplified method that estimates the states and the state transition probabilities of the model from device measurements. We show that such a memristor model, generally corresponds to an absorbing Markov chain, the physical implications of which are also discussed. We apply this modelling methodology to real-world Pt/TiO2/Pt memristors and present results that validate its effectiveness in capturing the stochastic features of these devices over various timescales.

Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware
accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of
neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.

Biological synapses store multiple memories on top of each other in a palimpsest fashion and at different time scales. Palimpsest consolidation is facilitated by the interaction of hidden biochemical processes governing synaptic efficacy during varying lifetimes. This arrangement allows idle memories to be temporarily overwritten without being forgotten, while previously unseen memories are used in the short term. While embedded artificial intelligence can greatly benefit from this functionality, a practical demonstration in hardware is missing. Here, we show how the intrinsic properties of metal-oxide volatile memristors emulate the processes supporting biological palimpsest consolidation. Our memristive synapses exhibit an expanded doubled capacity and protect a consolidated memory while up to hundreds of uncorrelated short-term memories temporarily overwrite it, without requiring specialized instructions. We further demonstrate this technology in the context of visual working memory. This showcases how emerging memory technologies can efficiently expand the capabilities of artificial intelligence hardware toward more generalized learning memories.

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

A memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.

Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device's resistance range to be between 1k and 10M with a minimum voltage range of 1.5V on the device.

Electrochemical metallization memory (ECM) devices have been made by sub-stoichiometric deposition of a tantalum oxide switching film (Ta2O5−x) using sputtering. We investigated the influence of zirconium as the active top electrode material in the lithographically fabricated ECM devices. A simple capacitor like (Pt/Zr/Ta2O5−x/Pt) structure represented the resistive switching memory. A cyclic voltammetry measurement demonstrated the electrochemical process of the memory device. The I–V characteristics of ECMs show stable bipolar resistive switching properties with reliable endurance and retention. The resistive switching mechanism results from the formation and rupture of a conductive filament characteristic of ECM. Our results suggest that Zr can be considered a potential active electrode in the ECMs for the next generation of nonvolatile nanoelectronics. We successfully showed that the ECM device can work under AC pulses to emulate the essential characteristics of an artificial synapse by further improvements.

Organic and perovskite solar cells (PSCs) have made significant strides in the last couple of years achieving high power conversion efficiencies (18% and 29%, respectively) and exceptional stability. Ultra-flexible and environmentally stable organic and PSCs can effectively operate under various illumination settings. Herein, novel device concepts that comprise photovoltaic cells alone or in tandem with batteries or supercapacitors, acting as the main power supply to another microelectronic component, enabling self-powered electronics for the Internet of Things (IoT) are reviewed. Emphasis is placed on the specific requirements posed by such applications to pave the way to large scale commercialization. The importance of supporting a greener IoT ecosystem by eliminating toxic materials and solvents in the device fabrication process is highlighted.

Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.

The insertion of a metal layer between an active electrode and a switching layer leads to the formation of a ternary oxide at the interface. The properties of this self-formed oxide are found to be dependent on the Gibbs free energy of oxide formation of the metal (Δ𝐺∘𝑓). We investigated the role of various ternary oxides in the switching behavior of conductive bridge random access memory (CBRAM) devices. The ternary oxide acts as a barrier layer that can limit the mobility of metal cations in the cell, promoting stable switching. However, too low (higher negative value) Δ𝐺∘𝑓 leads to severe trade-offs; the devices require high operation current and voltages to exhibit switching behavior and low memory window (on/off) ratio. We propose that choosing a metal layer having appropriate Δ𝐺∘𝑓 is crucial in achieving reliable CBRAM devices.

Various on-workstation neural-spike-based brain machine interface (BMI) systems have reached the point of in-human trials, but on-node and on-implant BMI systems are still under exploration. Such systems are constrained by the area and battery. Researchers should consider the algorithm complexity, available resources, power budgets, CMOS technologies, and the choice of platforms when designing BMI systems. However, the effect of these factors is currently still unclear.Approaches.Here we have proposed a novel real-time 128 channel spike detection algorithm and optimised it on microcontroller (MCU) and field programmable gate array (FPGA) platforms towards consuming minimal power and memory/resources. It is presented as a use case to explore the different considerations in system design.Main results.The proposed spike detection algorithm achieved over 97% sensitivity and a smaller than 3% false detection rate. The MCU implementation occupies less than 3 KB RAM and consumes 31.5 µW ch-1. The FPGA platform only occupies 299 logic cells and 3 KB RAM for 128 channels and consumes 0.04 µW ch-1.Significance.On the spike detection algorithm front, we have eliminated the processing bottleneck by reducing the dynamic power consumption to lower than the hardware static power, without sacrificing detection performance. More importantly, we have explored the considerations in algorithm and hardware design with respect to scalability, portability, and costs. These findings can facilitate and guide the future development of real-time on-implant neural signal processing platforms.

Emerging two terminal nanoscale memory devices, known as memristors, have over the past decade demonstrated great potential for implementing energy efficient neuro-inspired computing architectures. As a result, a wide-range of technologies have been developed that in turn are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors' attributes in novel neuro-inspired topologies. In this paper, we present NeuroPack, a modular, algorithm level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to chose from a variety of neuron models, learning rules and memristors models. Its hierarchical structure, empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameters options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.

Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (= speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity.

In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds.

Resistive RAM (RRAM) or memristors are a class of electronic device whose resistance depends on voltage history. The changes in resistance can be divided into two categories, volatile and non-volatile. To date, the characteristics of non-volatile switching have been explored extensively with volatile switching behaviour still remaining more obscure. Here we investigate the temperature effects on TiOx based memristor volatility, and integrate these observations into a previously developed model for volatile switching. We show how device temperature affects the magnitude of the volatile resistive state in response to input stimulation, as well as the corresponding relaxation time constant. Importantly, these effects are polarity dependent. This work is part of an effort towards building a more comprehensive model of RRAM behaviour covering volatile and non-volatile phenomena as well as various environmental effects on them.

A memristor compact model, which can both capture state volatility and describe short-term and long-term memory transitions, is introduced. The model is based on an energy landscape acting as a pseudo-potential which generates the driving forces for configurational changes. A stable conductance change in this model is implemented through a sequence of transitions between states of plasticity occurring over different time-scales. Such transitions also modify the detail of the pseudopotential landscape, this way altering the probability distribution of subsequent state-change events. This approach departs from the usual method of applying perfectly non-volatile increments on the state variable. The model has been coded in Verilog-A, so that it can be used in many popular SPICE engines. The proposed model is semi-quantitatively fitted to measurements taken on Pt/TiO2/Pt stack memristor devices.

This paper presents an integrated memristive memory (RRAM) capable of storing 4 states in each memory location. RRAM advantages include non-volatility, low power consumption, high speed, and compatibility with existing CMOS technology. More importantly, RRAM has the potential to achieve multi-state storage on a single memory cell. Nevertheless, there is no multi-state RRAM integrated with CMOS technology that has been reported in literature. In this work, we propose a precise write-in and readout circuit for multi-state memristive memory. The memory is designed over a crossbar array architecture, a 1 transistor 1 memristor (1T1R) topology is employed to eliminate sneak-path currents. Data readout is carried out by two amplifiers and a 12-bit successive approximation analog to digital converter (SAR ADC). The RRAM successfully writes and reads 2-bit information by dividing the resistance of the memristor (memristance) into 4 states of 28kΩ±2kΩ(11),37kΩ±3kΩ(10),46kΩ±4kΩ(01) , and 56kΩ±4kΩ(00) . The total area of the proposed RRAM is 0.92 mm 2 . The RRAM is prepared to be made in TSMC 0.18μm process.

A route toward processable n-type terpolymers is presented herein based on the random donor–acceptor–donor–acceptor (D–A1)-(D–A2) molecular configuration. Carbazole is utilized as the electron donating unit (D) combined with perylene diimide (PDI) as the first electron acceptor (A1) and either one of two different benzothiadiazole (BTZ) derivatives (di-thienyl substituted-BTZ and di-3,4-ethylenedioxythienyl substituted-BTZ) as the second electron accepting unit (A2). Increasing the content of the PDI co-monomer resulted in terpolymers of higher molecular weights, enhanced solubility, and stronger n-type character. The physicochemical properties of the random PDI-Cz-BTZ derivatives are fine-tuned based on the feed ratio of the co-monomers. Photodiode devices were demonstrated, having photoactive layers composed of the rich in PDI terpolymer, namely, P4 having a 75% PDI content, and the PCE10 electron donor, under various ratios. For a range of P4 blend compositions, UV–Vis, is spectroscopy confirmed the strong absorption of the blend films across the 350–800 nm spectral region, and AFM imaging verified their low surface roughness. The study of the electro-optical device properties identified the 1:2 blending ratio as the optimum PCE10:P4 combination for maximum charge photogeneration efficiency. Despite the relatively deep LUMO energy of the n-type P4 terpolymer (ELUMO = −4.04 eV), trap-induced charge recombination losses were found to limit the PCE10:P4 photodiode performance. Unipolar devices of the P4-alone exhibited hole and electron mobility values of 2.2 × 10–4 and 6.3 × 10–5 cm2 V–1 s–1, respectively.