Flexible electronics have seen extensive research over the past years due to their potential stretchability and adaptability to non-flat surfaces. They are key to realizing low-power sensors and circuits for wearable electronics and Internet of Things (IoT) applications. Semiconducting metal-oxides are a prime candidate for implementing flexible electronics as their conformal deposition methods lend themselves to the idiosyncrasies of non-rigid substrates. They are also a major component for the development of resistive memories (memristors) and as such their monolithic integration with thin film electronics has the potential to lead to novel all-metal-oxide devices combining memory and computing on a single node. This review focuses on exploring the recent advances across all these fronts starting from types of suitable substrates and their mechanical properties, different types of fabrication methods for thin film transistors and memristors applicable to flexible substrates (vacuum- or solution-based), applications and comparison with rigid substrates while additionally delving into matters associated with their monolithic integration.

Memristive technologies promise to have a large impact on modern electronics, particularly in the areas of reconfigurable computing and AI hardware. Meanwhile, the evolution of memristive materials alongside the technological progress is opening application perspectives also in the biomedical field, particularly for implantable and lab-on-a-chip devices where advanced sensing technologies generate a large amount of data. Memristive devices are emerging as bioelectronic links merging biosensing with computation, acting as physical processors of analogue signals or in the framework of advanced digital computing architectures. We review recent developments on the processing of electrical neural signals, as well as on transduction and processing of chemical biomarkers of neural and endocrine functions. We conclude with a critical perspective on the future applicability of memristive devices as pivotal building blocks in Bio-AI fusion concepts and bionic schemes.

Latent representations are a necessary component of cognitive artificial intelligence (AI) systems. Here, we investigate the performance of various sequential clustering algorithms on latent representations generated by autoencoder and convolutional neural network (CNN) models. We also introduce a new algorithm, called Collage, which brings views and concepts into sequential clustering to bridge the gap with cognitive AI. The algorithm is designed to reduce memory requirements, numbers of operations (which translate into hardware clock cycles) and thus improve energy, speed and area performance of an accelerator for running said algorithm. Results show that plain autoencoders produce latent representations which have large inter-cluster overlaps. CNNs are shown to solve this problem, however introduce their own problems in the context of generalized cognitive pipelines.

The deployment of FPGAs in cloud data centers has entailed new security concerns. Although several defensive mechanisms are employed to detect and prevent malicious designs, a health monitoring tool can warn cloud service providers about the failure of implemented defensive fences. This PhD project aims to monitor the health status of internal FPGA resources by performing a precise timing characterization.

Neural activity recording system promotes the development of diagnostic and therapeutic programs and neuroscience research. Direct recordings of neural signals from the brain have helped scientists access to study and unlock the secrets of neural coding gradually. This can be realised by applying implantable neural recording systems to monitor and record neural signals. Then, the neural information can be transmitted to the external device for processing, storage or application. However, the power consumption of the neural recording system is the primary constraint to monitoring large groups of neurons. It leads the development of neural recording systems in two directions: 'high-channel-count but wired' and 'wireless but low-channel-count'. To address the power issue, we proposed a neural front-end that aims to detect neural spikes by thresholding and output as one-bit digital data so that the afterwards processing can only work on spikes rather than processing all the data points. The most significant feature is that we induce memristors as trimming devices to tune the threshold voltage for spike detection. Meanwhile, it contributes to rejecting up to 50mV DC offset from electrodes. The measurement presents that the memristor-based pre-amplifier is capable of achieving above 95% spike detection accuracy with hundreds of nanowatt power consumption per channel. This design indicates a promising approach to conduct spike-detection on-chip with low power consumption and demonstrates the potential of a hybrid memristor/CMOS circuit for power-efficient large-scale neural interfacing application.

The memristor is an innovative passive electrical device that has gained popularity in recent years as a potential candidate for next-generation non-volatile memory (NVM) and analog computing. This popularity stems from the memristor’s ability to store information in a manner that is inaccessible to external power sources. It is possible to electrically modify the resistance state, and this change will be retained even after the external bias has been removed. This is a distinctive electrical characteristic of the device. In this paper, we present a comprehensive presentation and illustration about SkyWater memristor device and model. A read/write operation for a standalone memristor (1R), and a 1 transistor 1 memristor (1T1R) were conducted. The RRAM successfully can be written and read 1-bit information by dividing the resistance of the memristor (memristance) into two states of RON=10.07 KΩ as a bit 1 and ROFF=3.38 MΩ as a bit 0.

Memristor memory has garnered more interest as a potential future non-volatile memory. One access transistor and one memristor (1T1R) cell structure can be utilized to eliminate the issue of sneak path current in crossbar-structured memristor memories. However, it has lower switching speed and high-power consumption. In this paper, a novel passive selectorless structure cell has been studied. One capacitor-One Memristor (1C1R) structure is proposed as a passive access device that can be controlled by the applied signal width. The 1C1R successfully writes and reads 1-bit information with two resistance value: 3.38MΩ as bit 0, and 10.07KΩ as a bit 1. 1C1R topology is proposed as a promising structure that has lower power consumption and faster switching speed compared to 1T1R. In addition, this work addresses the readout technique with 1C1R structure. The RRAM is implemented by SkyWater Verilog-A model.