Electro-forming capable ReRAM characterisation chip

MELITA chip family

Conduction mechanisms at distinct resistive levels of Pt/TiO2-x/Pt memristors Electrical characteristics of interfacial barriers at metal—TiO2 contacts An electrical characterisation methodology for identifying the switching mechanism in TiO2 memristive stacks

Process maturity: Stable SnOx can behave as either n-type or p-type semiconductor depending on the defect type and density. It can be used for both RRAM and TFTs, therefore, it is a suitable material for CMOS integration and for all oxide 1T1R devices. The prepared SnOx-based RRAM devices show analog switching and either non-volatile or volatile behaviour depending on the electrode materials.

Process maturity: Stable The device is formingless and has low voltage operation. Similar behaviour can be found with devices made with thinner ZnO layer (>30 nm); however, the On/Off ratio is smaller. Thinner devices exhibit volatile characteristics. Nevertheless, the device yield needs to be improved.

Process maturity: Stable D1 having small size cell (SA5) exhibits stable switching. However, the instability exhibited in larger cell (SA60) can be avoided by introducing Cr barrier layer (D2).

Neuropack: an algorithm-level simulator for memristor-empowered neuro-inspired computing

Process maturity: Stable This is a variation of the TiOx standard recipe aimed to address volatility issues to otherwise non-volatile devices. It is realised as a thin AlOx layer introduced between the active layer and top electrode. The layer is thin enough as to amount as an interfacial modification rather that true bilayer devices. Devices exhibit lower volatility which eventually results in satisfactory multi-bit performance.

A Data-Driven Verilog-A ReRAM Model

Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.

RRAM technology has experienced explosive growth in the next generation of nano-electronics, with multiple device structures being developed for a wide range of applications. However, this technology is only accessible to a handful of circuit designers, scientists and researchers where in-house fabrication and funds are available. Thus, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain such that circuit design and validation can be done before it is laid onto the wafer and integrated with CMOS.

Process maturity: Stable TiOx-based memristors are the basic devices fabricated by our lab and have been used for many different papers and applications. They provide reliable non-volatile or volatile behaviour depending on the choice of electrodes and forming procedure. Depending on forming method volatile behaviour is still present even in formed devices. Items with (*) below indicate possibility for CMOS integration.

Stand-alone, desktop, versatile array control system. Comes with dedicated open-source UI running on PC/MAC for all your RRAM measurement needs. Built upon 6 generations of increasingly complex instruments for characterising crossbars of emerging non-volatile memories. Includes current cut-off and I-V curve tracing capability.

Watch the video featuring charge recovery computing and the potential of the first adiabatic neuro network demonstrator chip